/** @file
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Copyright (c) 2016 Linaro Ltd.
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Copyright (c) 2016 Hisilicon Limited.
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Uefi.h>
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#include <Library/BaseLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/DebugLib.h>
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#include <Library/DevicePathLib.h>
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#include <Library/DmaLib.h>
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#include <Library/IoLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/PcdLib.h>
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#include <Library/TimerLib.h>
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#include <Library/UefiBootServicesTableLib.h>
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#include <Library/UefiLib.h>
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#include <Protocol/PlatformSasProtocol.h>
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#include <Protocol/ScsiPassThruExt.h>
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#include <IndustryStandard/Scsi.h>
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#define READ_REG32(Base, Offset) MmioRead32 ((Base) + (Offset))
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#define WRITE_REG32(Base, Offset, Val) MmioWrite32 ((Base) + (Offset), (Val))
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#define PHY_READ_REG32(Base, Offset, phy) MmioRead32 ((Base) + (Offset) + 0x400 * (phy))
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#define PHY_WRITE_REG32(Base, Offset, phy, Val) MmioWrite32 ((Base) + (Offset) + 0x400 * (phy), (Val))
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#define DLVRY_QUEUE_ENABLE 0x0
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#define IOST_BASE_ADDR_LO 0x8
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#define IOST_BASE_ADDR_HI 0xc
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#define ITCT_BASE_ADDR_LO 0x10
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#define ITCT_BASE_ADDR_HI 0x14
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#define BROKEN_MSG_ADDR_LO 0x18
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#define BROKEN_MSG_ADDR_HI 0x1c
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#define PHY_CONTEXT 0x20
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#define PHY_PORT_NUM_MA 0x28
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#define HGC_TRANS_TASK_CNT_LIMIT 0x38
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#define AXI_AHB_CLK_CFG 0x3c
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#define HGC_SAS_TXFAIL_RETRY_CTRL 0x84
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#define HGC_GET_ITV_TIME 0x90
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#define DEVICE_MSG_WORK_MODE 0x94
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#define I_T_NEXUS_LOSS_TIME 0xa0
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#define BUS_INACTIVE_LIMIT_TIME 0xa8
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#define REJECT_TO_OPEN_LIMIT_TIME 0xac
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#define CFG_AGING_TIME 0xbc
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#define HGC_DFX_CFG2 0xc0
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#define FIS_LIST_BADDR_L 0xc4
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#define CFG_1US_TIMER_TRSH 0xcc
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#define CFG_SAS_CONFIG 0xd4
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#define INT_COAL_EN 0x1bc
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#define OQ_INT_COAL_TIME 0x1c0
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#define OQ_INT_COAL_CNT 0x1c4
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#define ENT_INT_COAL_TIME 0x1c8
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#define ENT_INT_COAL_CNT 0x1cc
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#define OQ_INT_SRC 0x1d0
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#define OQ_INT_SRC_MSK 0x1d4
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#define ENT_INT_SRC1 0x1d8
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#define ENT_INT_SRC2 0x1dc
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#define ENT_INT_SRC_MSK1 0x1e0
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#define ENT_INT_SRC_MSK2 0x1e4
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#define SAS_ECC_INTR_MSK 0x1ec
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#define HGC_ERR_STAT_EN 0x238
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#define DLVRY_Q_0_BASE_ADDR_LO 0x260
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#define DLVRY_Q_0_BASE_ADDR_HI 0x264
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#define DLVRY_Q_0_DEPTH 0x268
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#define DLVRY_Q_0_WR_PTR 0x26c
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#define DLVRY_Q_0_RD_PTR 0x270
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#define COMPL_Q_0_BASE_ADDR_LO 0x4e0
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#define COMPL_Q_0_BASE_ADDR_HI 0x4e4
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#define COMPL_Q_0_DEPTH 0x4e8
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#define COMPL_Q_0_WR_PTR 0x4ec
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#define COMPL_Q_0_RD_PTR 0x4f0
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#define AXI_CFG 0x5100
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#define PORT_BASE 0x800
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#define PHY_CFG (PORT_BASE + 0x0)
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#define PHY_CFG_ENA_OFF 0
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#define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF)
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#define PHY_CFG_DC_OPT_OFF 2
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#define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF)
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#define PROG_PHY_LINK_RATE (PORT_BASE + 0xc)
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#define PHY_CTRL (PORT_BASE + 0x14)
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#define PHY_CTRL_RESET BIT0
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#define PHY_RATE_NEGO (PORT_BASE + 0x30)
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#define PHY_PCN (PORT_BASE + 0x44)
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#define SL_TOUT_CFG (PORT_BASE + 0x8c)
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#define SL_CONTROL (PORT_BASE + 0x94)
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#define SL_CONTROL_NOTIFY_EN BIT0
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#define TX_ID_DWORD0 (PORT_BASE + 0x9c)
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#define TX_ID_DWORD1 (PORT_BASE + 0xa0)
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#define TX_ID_DWORD2 (PORT_BASE + 0xa4)
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#define TX_ID_DWORD3 (PORT_BASE + 0xa8)
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#define TX_ID_DWORD4 (PORT_BASE + 0xaC)
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#define TX_ID_DWORD5 (PORT_BASE + 0xb0)
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#define TX_ID_DWORD6 (PORT_BASE + 0xb4)
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#define RX_IDAF_DWORD3 (PORT_BASE + 0xd0)
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#define RX_IDAF_DWORD4 (PORT_BASE + 0xd4)
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#define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc)
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#define DONE_RECEIVED_TIME (PORT_BASE + 0x12c)
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#define CON_CFG_DRIVER (PORT_BASE + 0x130)
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#define PHY_CONFIG2 (PORT_BASE + 0x1a8)
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#define PHY_CONFIG2_FORCE_TXDEEMPH_OFF 3
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#define PHY_CONFIG2_FORCE_TXDEEMPH_MSK (0x1 << PHY_CONFIG2_FORCE_TXDEEMPH_OFF)
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#define CHL_INT_COAL_EN (PORT_BASE + 0x1d0)
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#define CHL_INT0 (PORT_BASE + 0x1b0)
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#define CHL_INT0_PHYCTRL_NOTRDY BIT0
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#define CHL_INT1 (PORT_BASE + 0x1b4)
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#define CHL_INT2 (PORT_BASE + 0x1b8)
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#define CHL_INT2_SL_PHY_ENA BIT6
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#define CHL_INT0_MSK (PORT_BASE + 0x1bc)
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#define CHL_INT0_MSK_PHYCTRL_NOTRDY BIT0
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#define CHL_INT1_MSK (PORT_BASE + 0x1c0)
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#define CHL_INT2_MSK (PORT_BASE + 0x1c4)
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#define DMA_TX_STATUS (PORT_BASE + 0x2d0)
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#define DMA_TX_STATUS_BUSY BIT0
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#define DMA_RX_STATUS (PORT_BASE + 0x2e8)
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#define DMA_RX_STATUS_BUSY BIT0
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#define QUEUE_CNT 32
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#define QUEUE_SLOTS 256
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#define SLOT_ENTRIES 8192
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#define PHY_CNT 8
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#define MAX_ITCT_ENTRIES 1
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// Completion header
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#define CMPLT_HDR_IPTT_OFF 0
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#define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF)
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#define BIT(x) (1 << x)
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// HW dma structures
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// Delivery queue header
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// dw0
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#define CMD_HDR_RESP_REPORT_OFF 5
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#define CMD_HDR_RESP_REPORT_MSK 0x20
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#define CMD_HDR_TLR_CTRL_OFF 6
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#define CMD_HDR_TLR_CTRL_MSK 0xc0
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#define CMD_HDR_PORT_OFF 17
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#define CMD_HDR_PORT_MSK 0xe0000
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#define CMD_HDR_PRIORITY_OFF 27
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#define CMD_HDR_PRIORITY_MSK 0x8000000
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#define CMD_HDR_MODE_OFF 28
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#define CMD_HDR_MODE_MSK 0x10000000
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#define CMD_HDR_CMD_OFF 29
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#define CMD_HDR_CMD_MSK 0xe0000000
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// dw1
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#define CMD_HDR_VERIFY_DTL_OFF 10
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#define CMD_HDR_VERIFY_DTL_MSK 0x400
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#define CMD_HDR_SSP_FRAME_TYPE_OFF 13
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#define CMD_HDR_SSP_FRAME_TYPE_MSK 0xe000
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#define CMD_HDR_DEVICE_ID_OFF 16
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#define CMD_HDR_DEVICE_ID_MSK 0xffff0000
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// dw2
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#define CMD_HDR_CFL_OFF 0
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#define CMD_HDR_CFL_MSK 0x1ff
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#define CMD_HDR_MRFL_OFF 15
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#define CMD_HDR_MRFL_MSK 0xff8000
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#define CMD_HDR_FIRST_BURST_OFF 25
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#define CMD_HDR_FIRST_BURST_MSK 0x2000000
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// dw3
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#define CMD_HDR_IPTT_OFF 0
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#define CMD_HDR_IPTT_MSK 0xffff
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// dw6
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#define CMD_HDR_DATA_SGL_LEN_OFF 16
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#define CMD_HDR_DATA_SGL_LEN_MSK 0xffff0000
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// Completion header
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#define CMPLT_HDR_IPTT_OFF 0
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#define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF)
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#define CMPLT_HDR_CMD_CMPLT_MSK BIT17
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#define CMPLT_HDR_ERR_RCRD_XFRD_MSK BIT18
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#define CMPLT_HDR_RSPNS_XFRD_MSK BIT19
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#define CMPLT_HDR_IO_CFG_ERR_MSK BIT27
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#define SENSE_DATA_PRES 26
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#define SGE_LIMIT 0x10000
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#define upper_32_bits(n) ((UINT32)(((n) >> 16) >> 16))
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#define lower_32_bits(n) ((UINT32)(n))
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#define MAX_TARGET_ID 4
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// Generic HW DMA host memory structures
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struct hisi_sas_cmd_hdr {
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UINT32 dw0;
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UINT32 dw1;
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UINT32 dw2;
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UINT32 transfer_tags;
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UINT32 data_transfer_len;
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UINT32 first_burst_num;
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UINT32 sg_len;
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UINT32 dw7;
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UINT64 cmd_table_addr;
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UINT64 sts_buffer_addr;
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UINT64 prd_table_addr;
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UINT64 dif_prd_table_addr;
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};
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struct hisi_sas_complete_hdr {
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UINT32 data;
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};
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struct hisi_sas_iost {
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UINT64 qw0;
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UINT64 qw1;
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UINT64 qw2;
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UINT64 qw3;
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};
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struct hisi_sas_itct {
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UINT64 qw0;
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UINT64 sas_addr;
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UINT64 qw2;
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UINT64 qw3;
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UINT64 qw4;
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UINT64 qw_sata_ncq0_3;
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UINT64 qw_sata_ncq7_4;
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UINT64 qw_sata_ncq11_8;
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UINT64 qw_sata_ncq15_12;
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UINT64 qw_sata_ncq19_16;
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UINT64 qw_sata_ncq23_20;
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UINT64 qw_sata_ncq27_24;
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UINT64 qw_sata_ncq31_28;
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UINT64 qw_non_ncq_iptt;
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UINT64 qw_rsvd0;
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UINT64 qw_rsvd1;
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};
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struct hisi_sas_breakpoint {
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UINT8 data[128];
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};
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struct hisi_sas_sge {
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UINT64 addr;
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UINT32 page_ctrl_0;
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UINT32 page_ctrl_1;
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UINT32 data_len;
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UINT32 data_off;
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};
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struct hisi_sas_sge_page {
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struct hisi_sas_sge sg[512];
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};
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struct hisi_sas_cmd {
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UINT8 cmd[128];
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};
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struct hisi_sas_sts {
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UINT32 status[260];
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};
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struct hisi_sas_slot {
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BOOLEAN used;
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};
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struct hisi_hba {
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struct hisi_sas_cmd_hdr *cmd_hdr[QUEUE_CNT];
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struct hisi_sas_complete_hdr *complete_hdr[QUEUE_CNT];
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struct hisi_sas_sge_page *sge[QUEUE_CNT];
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struct hisi_sas_sts *status_buf[QUEUE_CNT];
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struct hisi_sas_cmd *command_table[QUEUE_CNT];
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struct hisi_sas_iost *iost;
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struct hisi_sas_itct *itct;
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struct hisi_sas_breakpoint *breakpoint;
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struct hisi_sas_slot *slots;
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UINT32 base;
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int queue;
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int port_id;
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UINT32 LatestTargetId;
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UINT64 LatestLun;
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};
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#pragma pack (1)
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typedef struct {
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VENDOR_DEVICE_PATH Vendor;
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UINT64 PhysBase;
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EFI_DEVICE_PATH_PROTOCOL End;
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} SAS_V1_TRANSPORT_DEVICE_PATH;
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#pragma pack ()
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typedef struct {
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UINT32 Signature;
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EFI_EXT_SCSI_PASS_THRU_MODE ExtScsiPassThruMode;
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EFI_EXT_SCSI_PASS_THRU_PROTOCOL ExtScsiPassThru;
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SAS_V1_TRANSPORT_DEVICE_PATH *DevicePath;
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struct hisi_hba *hba;
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EFI_EVENT TimerEvent;
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} SAS_V1_INFO;
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#define SAS_DEVICE_SIGNATURE SIGNATURE_32 ('S','A','S','0')
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#define SAS_FROM_PASS_THRU(a) CR (a, SAS_V1_INFO, ExtScsiPassThru, SAS_DEVICE_SIGNATURE)
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STATIC EFI_STATUS prepare_cmd (
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struct hisi_hba *hba,
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EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET *Packet
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)
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{
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struct hisi_sas_slot *slot;
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struct hisi_sas_cmd_hdr *hdr;
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struct hisi_sas_sge_page *sge;
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struct hisi_sas_sts *sts;
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struct hisi_sas_cmd *cmd;
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EFI_SCSI_SENSE_DATA *SensePtr = Packet->SenseData;
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VOID *Buffer = NULL;
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UINTN BufferSize = 0;
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int queue = hba->queue;
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UINT32 r, w = 0, slot_idx = 0;
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UINT32 base = hba->base;
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UINT8 *p;
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EFI_PHYSICAL_ADDRESS BufferAddress;
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EFI_STATUS Status = EFI_SUCCESS;
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VOID *BufferMap = NULL;
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DMA_MAP_OPERATION DmaOperation = MapOperationBusMasterCommonBuffer;
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while (1) {
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w = READ_REG32(base, DLVRY_Q_0_WR_PTR + (queue * 0x14));
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r = READ_REG32(base, DLVRY_Q_0_RD_PTR + (queue * 0x14));
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slot_idx = queue * QUEUE_SLOTS + w;
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slot = &hba->slots[slot_idx];
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if (slot->used || (r == (w+1) % QUEUE_SLOTS)) {
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queue = (queue + 1) % QUEUE_CNT;
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if (queue == hba->queue) {
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DEBUG ((EFI_D_ERROR, "could not find free slot\n"));
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return EFI_NOT_READY;
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}
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continue;
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}
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break;
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}
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hdr = &hba->cmd_hdr[queue][w];
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cmd = &hba->command_table[queue][w];
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sts = &hba->status_buf[queue][w];
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sge = &hba->sge[queue][w];
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ZeroMem (cmd, sizeof (struct hisi_sas_cmd));
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ZeroMem (sts, sizeof (struct hisi_sas_sts));
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if (SensePtr)
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ZeroMem (SensePtr, sizeof (EFI_SCSI_SENSE_DATA));
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slot->used = TRUE;
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hba->queue = (queue + 1) % QUEUE_CNT;
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// Only consider ssp
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hdr->dw0 = (1 << CMD_HDR_RESP_REPORT_OFF) |
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(0x2 << CMD_HDR_TLR_CTRL_OFF) |
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(hba->port_id << CMD_HDR_PORT_OFF) |
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(1 << CMD_HDR_MODE_OFF) |
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(1 << CMD_HDR_CMD_OFF);
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hdr->dw1 = 1 << CMD_HDR_VERIFY_DTL_OFF;
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hdr->dw1 |= 0 << CMD_HDR_DEVICE_ID_OFF;
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hdr->dw2 = 0x83000d;
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hdr->transfer_tags = slot_idx << CMD_HDR_IPTT_OFF;
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if (Packet->DataDirection == EFI_EXT_SCSI_DATA_DIRECTION_READ) {
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Buffer = Packet->InDataBuffer;
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BufferSize = Packet->InTransferLength;
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if (Buffer) {
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hdr->dw1 |= 1 << CMD_HDR_SSP_FRAME_TYPE_OFF;
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DmaOperation = MapOperationBusMasterWrite;
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}
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} else if (Packet->DataDirection == EFI_EXT_SCSI_DATA_DIRECTION_WRITE) {
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Buffer = Packet->OutDataBuffer;
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BufferSize = Packet->OutTransferLength;
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if (Buffer) {
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DmaOperation = MapOperationBusMasterRead;
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hdr->dw1 |= 2 << CMD_HDR_SSP_FRAME_TYPE_OFF;
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}
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} else {
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hdr->dw1 |= 0 << CMD_HDR_SSP_FRAME_TYPE_OFF;
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}
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hdr->data_transfer_len = BufferSize;
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hdr->cmd_table_addr = (UINT64)cmd;
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hdr->sts_buffer_addr = (UINT64)sts;
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CopyMem (&cmd->cmd[36], Packet->Cdb, Packet->CdbLength);
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if (Buffer != NULL) {
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struct hisi_sas_sge *sg;
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UINT32 remain, len, pos = 0, i = 0;
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Status = DmaMap (DmaOperation, Buffer, &BufferSize, &BufferAddress, &BufferMap);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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remain = len = BufferSize;
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while (remain) {
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if (len > SGE_LIMIT)
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len = SGE_LIMIT;
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sg = &sge->sg[i];
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sg->addr = (UINT64)(BufferAddress + pos);
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sg->page_ctrl_0 = sg->page_ctrl_1 = 0;
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sg->data_len = len;
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sg->data_off = 0;
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remain -= len;
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pos += len;
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len = remain;
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i++;
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}
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hdr->prd_table_addr = (UINT64)sge;
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hdr->sg_len = i << CMD_HDR_DATA_SGL_LEN_OFF;
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}
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// Ensure descriptor effective before start dma
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MemoryFence();
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// Start dma
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WRITE_REG32(base, DLVRY_Q_0_WR_PTR + queue * 0x14, ++w % QUEUE_SLOTS);
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// Wait for dma complete
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while (slot->used) {
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if (READ_REG32(base, OQ_INT_SRC) & BIT(queue)) {
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struct hisi_sas_complete_hdr *complete_hdr;
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UINT32 data, rd;
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rd = READ_REG32(base, COMPL_Q_0_RD_PTR + (0x14 * queue));
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complete_hdr = &hba->complete_hdr[queue][rd];
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data = complete_hdr->data;
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// Check whether dma transfer error
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if ((data & CMPLT_HDR_ERR_RCRD_XFRD_MSK) &&
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!(data & CMPLT_HDR_RSPNS_XFRD_MSK)) {
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DEBUG ((EFI_D_VERBOSE, "sas retry data=0x%x\n", data));
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DEBUG ((EFI_D_VERBOSE, "sts[0]=0x%x\n", sts->status[0]));
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DEBUG ((EFI_D_VERBOSE, "sts[1]=0x%x\n", sts->status[1]));
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DEBUG ((EFI_D_VERBOSE, "sts[2]=0x%x\n", sts->status[2]));
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Status = EFI_NOT_READY;
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// wait 1 second and retry, some disk need long time to be ready
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// and ScsiDisk treat retry over 3 times as error
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MicroSecondDelay(1000000);
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}
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// Update read point
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WRITE_REG32(base, COMPL_Q_0_RD_PTR + (0x14 * queue), w);
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// Clear int
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WRITE_REG32(base, OQ_INT_SRC, BIT(queue));
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slot->used = FALSE;
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break;
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}
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// Wait for status change in polling
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NanoSecondDelay (100);
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}
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if (BufferMap)
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DmaUnmap (BufferMap);
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p = (UINT8 *)&sts->status[0];
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if (p[SENSE_DATA_PRES]) {
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// Disk not ready normal return for ScsiDiskTestUnitReady do next try
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SensePtr->Sense_Key = EFI_SCSI_SK_NOT_READY;
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SensePtr->Addnl_Sense_Code = EFI_SCSI_ASC_NOT_READY;
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SensePtr->Addnl_Sense_Code_Qualifier = EFI_SCSI_ASCQ_IN_PROGRESS;
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// wait 1 second for disk spin up, refer drivers/scsi/sd.c
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MicroSecondDelay(1000000);
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}
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return Status;
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}
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STATIC VOID hisi_sas_v1_init(struct hisi_hba *hba, PLATFORM_SAS_PROTOCOL *plat)
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{
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int i, j;
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UINT32 val, base = hba->base;
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// Reset
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for (i = 0; i < PHY_CNT; i++) {
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UINT32 phy_ctrl = PHY_READ_REG32(base, PHY_CTRL, i);
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phy_ctrl |= PHY_CTRL_RESET;
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PHY_WRITE_REG32(base, PHY_CTRL, i, phy_ctrl);
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}
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// spec says safe to wait 50us after reset
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MicroSecondDelay(50);
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// Ensure DMA tx & rx idle
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for (i = 0; i < PHY_CNT; i++) {
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UINT32 dma_tx_status, dma_rx_status;
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for (j = 0; j < 100; j++) {
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dma_tx_status = PHY_READ_REG32(base, DMA_TX_STATUS, i);
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dma_rx_status = PHY_READ_REG32(base, DMA_RX_STATUS, i);
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if (!(dma_tx_status & DMA_TX_STATUS_BUSY) &&
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!(dma_rx_status & DMA_RX_STATUS_BUSY))
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break;
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// Wait for status change in polling
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NanoSecondDelay (100);
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}
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}
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// Ensure axi bus idle
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for (j = 0; j < 100; j++) {
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UINT32 axi_status = READ_REG32(base, AXI_CFG);
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if (axi_status == 0)
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break;
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// Wait for status change in polling
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NanoSecondDelay (100);
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}
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plat->Init(plat);
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WRITE_REG32(base, DLVRY_QUEUE_ENABLE, 0xffffffff);
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WRITE_REG32(base, HGC_TRANS_TASK_CNT_LIMIT, 0x11);
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WRITE_REG32(base, DEVICE_MSG_WORK_MODE, 0x1);
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WRITE_REG32(base, HGC_SAS_TXFAIL_RETRY_CTRL, 0x1ff);
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WRITE_REG32(base, HGC_ERR_STAT_EN, 0x401);
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WRITE_REG32(base, CFG_1US_TIMER_TRSH, 0x64);
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WRITE_REG32(base, HGC_GET_ITV_TIME, 0x1);
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WRITE_REG32(base, I_T_NEXUS_LOSS_TIME, 0x64);
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WRITE_REG32(base, BUS_INACTIVE_LIMIT_TIME, 0x2710);
|
WRITE_REG32(base, REJECT_TO_OPEN_LIMIT_TIME, 0x1);
|
WRITE_REG32(base, CFG_AGING_TIME, 0x7a12);
|
WRITE_REG32(base, HGC_DFX_CFG2, 0x9c40);
|
WRITE_REG32(base, FIS_LIST_BADDR_L, 0x2);
|
WRITE_REG32(base, INT_COAL_EN, 0xc);
|
WRITE_REG32(base, OQ_INT_COAL_TIME, 0x186a0);
|
WRITE_REG32(base, OQ_INT_COAL_CNT, 1);
|
WRITE_REG32(base, ENT_INT_COAL_TIME, 0x1);
|
WRITE_REG32(base, ENT_INT_COAL_CNT, 0x1);
|
WRITE_REG32(base, OQ_INT_SRC, 0xffffffff);
|
WRITE_REG32(base, ENT_INT_SRC1, 0xffffffff);
|
WRITE_REG32(base, ENT_INT_SRC_MSK1, 0);
|
WRITE_REG32(base, ENT_INT_SRC2, 0xffffffff);
|
WRITE_REG32(base, ENT_INT_SRC_MSK2, 0);
|
WRITE_REG32(base, SAS_ECC_INTR_MSK, 0);
|
WRITE_REG32(base, AXI_AHB_CLK_CFG, 0x2);
|
WRITE_REG32(base, CFG_SAS_CONFIG, 0x22000000);
|
|
for (i = 0; i < PHY_CNT; i++) {
|
PHY_WRITE_REG32(base, PROG_PHY_LINK_RATE, i, 0x88a);
|
PHY_WRITE_REG32(base, PHY_CONFIG2, i, 0x7c080);
|
PHY_WRITE_REG32(base, PHY_RATE_NEGO, i, 0x415ee00);
|
PHY_WRITE_REG32(base, PHY_PCN, i, 0x80a80000);
|
PHY_WRITE_REG32(base, SL_TOUT_CFG, i, 0x7d7d7d7d);
|
PHY_WRITE_REG32(base, DONE_RECEIVED_TIME, i, 0x0);
|
PHY_WRITE_REG32(base, RXOP_CHECK_CFG_H, i, 0x1000);
|
PHY_WRITE_REG32(base, DONE_RECEIVED_TIME, i, 0);
|
PHY_WRITE_REG32(base, CON_CFG_DRIVER, i, 0x13f0a);
|
PHY_WRITE_REG32(base, CHL_INT_COAL_EN, i, 3);
|
PHY_WRITE_REG32(base, DONE_RECEIVED_TIME, i, 8);
|
}
|
|
for (i = 0; i < QUEUE_CNT; i++) {
|
WRITE_REG32(base, DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14), upper_32_bits((UINT64)(hba->cmd_hdr[i])));
|
WRITE_REG32(base, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14), lower_32_bits((UINT64)(hba->cmd_hdr[i])));
|
WRITE_REG32(base, DLVRY_Q_0_DEPTH + (i * 0x14), QUEUE_SLOTS);
|
|
WRITE_REG32(base, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14), upper_32_bits((UINT64)(hba->complete_hdr[i])));
|
WRITE_REG32(base, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14), lower_32_bits((UINT64)(hba->complete_hdr[i])));
|
WRITE_REG32(base, COMPL_Q_0_DEPTH + (i * 0x14), QUEUE_SLOTS);
|
}
|
|
WRITE_REG32(base, ITCT_BASE_ADDR_LO, lower_32_bits((UINT64)(hba->itct)));
|
WRITE_REG32(base, ITCT_BASE_ADDR_HI, upper_32_bits((UINT64)(hba->itct)));
|
|
WRITE_REG32(base, IOST_BASE_ADDR_LO, lower_32_bits((UINT64)(hba->iost)));
|
WRITE_REG32(base, IOST_BASE_ADDR_HI, upper_32_bits((UINT64)(hba->iost)));
|
|
WRITE_REG32(base, BROKEN_MSG_ADDR_LO, lower_32_bits((UINT64)(hba->breakpoint)));
|
WRITE_REG32(base, BROKEN_MSG_ADDR_HI, upper_32_bits((UINT64)(hba->breakpoint)));
|
|
for (i = 0; i < PHY_CNT; i++) {
|
// Clear interrupt status
|
val = PHY_READ_REG32(base, CHL_INT0, i);
|
PHY_WRITE_REG32(base, CHL_INT0, i, val);
|
val = PHY_READ_REG32(base, CHL_INT1, i);
|
PHY_WRITE_REG32(base, CHL_INT1, i, val);
|
val = PHY_READ_REG32(base, CHL_INT2, i);
|
PHY_WRITE_REG32(base, CHL_INT2, i, val);
|
|
// Bypass chip bug mask abnormal intr
|
PHY_WRITE_REG32(base, CHL_INT0_MSK, i, 0x3fffff & ~CHL_INT0_MSK_PHYCTRL_NOTRDY);
|
}
|
|
// Init phy
|
for (i = 0; i < PHY_CNT; i++) {
|
PHY_WRITE_REG32(base, TX_ID_DWORD0, i, 0x10010e00);
|
PHY_WRITE_REG32(base, TX_ID_DWORD1, i, 0x16);
|
PHY_WRITE_REG32(base, TX_ID_DWORD2, i, 0x20880150);
|
PHY_WRITE_REG32(base, TX_ID_DWORD3, i, 0x16);
|
PHY_WRITE_REG32(base, TX_ID_DWORD4, i, 0x20880150);
|
PHY_WRITE_REG32(base, TX_ID_DWORD5, i, 0x0);
|
|
val = PHY_READ_REG32(base, PHY_CFG, i);
|
val &= ~PHY_CFG_DC_OPT_MSK;
|
val |= 1 << PHY_CFG_DC_OPT_OFF;
|
PHY_WRITE_REG32(base, PHY_CFG, i, val);
|
|
val = PHY_READ_REG32(base, PHY_CONFIG2, i);
|
val &= ~PHY_CONFIG2_FORCE_TXDEEMPH_MSK;
|
PHY_WRITE_REG32(base, PHY_CONFIG2, i, val);
|
|
val = PHY_READ_REG32(base, PHY_CFG, i);
|
val |= PHY_CFG_ENA_MSK;
|
PHY_WRITE_REG32(base, PHY_CFG, i, val);
|
}
|
}
|
|
STATIC VOID sas_init(SAS_V1_INFO *SasV1Info, PLATFORM_SAS_PROTOCOL *plat)
|
{
|
struct hisi_hba *hba = SasV1Info->hba;
|
int i, s;
|
|
for (i = 0; i < QUEUE_CNT; i++) {
|
s = sizeof(struct hisi_sas_cmd_hdr) * QUEUE_SLOTS;
|
DmaAllocateBuffer (EfiBootServicesData, EFI_SIZE_TO_PAGES (s), (VOID *)&hba->cmd_hdr[i]);
|
ASSERT (hba->cmd_hdr[i] != NULL);
|
ZeroMem (hba->cmd_hdr[i], s);
|
|
s = sizeof(struct hisi_sas_complete_hdr) * QUEUE_SLOTS;
|
DmaAllocateBuffer (EfiBootServicesData, EFI_SIZE_TO_PAGES (s), (VOID *)&hba->complete_hdr[i]);
|
ASSERT (hba->complete_hdr[i] != NULL);
|
ZeroMem (hba->complete_hdr[i], s);
|
|
s = sizeof(struct hisi_sas_sts) * QUEUE_SLOTS;
|
DmaAllocateBuffer (EfiBootServicesData, EFI_SIZE_TO_PAGES (s), (VOID *)&hba->status_buf[i]);
|
ASSERT (hba->status_buf[i] != NULL);
|
ZeroMem (hba->status_buf[i], s);
|
|
s = sizeof(struct hisi_sas_cmd) * QUEUE_SLOTS;
|
DmaAllocateBuffer (EfiBootServicesData, EFI_SIZE_TO_PAGES (s), (VOID *)&hba->command_table[i]);
|
ASSERT (hba->command_table[i] != NULL);
|
ZeroMem (hba->command_table[i], s);
|
|
s = sizeof(struct hisi_sas_sge_page) * QUEUE_SLOTS;
|
DmaAllocateBuffer (EfiBootServicesData, EFI_SIZE_TO_PAGES (s), (VOID *)&hba->sge[i]);
|
ASSERT (hba->sge[i] != NULL);
|
ZeroMem (hba->sge[i], s);
|
}
|
|
s = SLOT_ENTRIES * sizeof(struct hisi_sas_iost);
|
DmaAllocateBuffer (EfiBootServicesData, EFI_SIZE_TO_PAGES (s), (VOID *)&hba->iost);
|
ASSERT (hba->iost != NULL);
|
ZeroMem (hba->iost, s);
|
|
s = SLOT_ENTRIES * sizeof(struct hisi_sas_breakpoint);
|
DmaAllocateBuffer (EfiBootServicesData, EFI_SIZE_TO_PAGES (s), (VOID *)&hba->breakpoint);
|
ASSERT (hba->breakpoint != NULL);
|
ZeroMem (hba->breakpoint, s);
|
|
s = MAX_ITCT_ENTRIES * sizeof(struct hisi_sas_itct);
|
DmaAllocateBuffer (EfiBootServicesData, EFI_SIZE_TO_PAGES (s), (VOID *)&hba->itct);
|
ASSERT (hba->itct != NULL);
|
ZeroMem (hba->itct, s);
|
|
hba->slots = AllocateZeroPool (SLOT_ENTRIES * sizeof(struct hisi_sas_slot));
|
ASSERT (hba->slots != NULL);
|
|
hisi_sas_v1_init(hba, plat);
|
}
|
|
STATIC
|
EFI_STATUS
|
EFIAPI
|
SasV1ExtScsiPassThruFunction (
|
IN EFI_EXT_SCSI_PASS_THRU_PROTOCOL *This,
|
IN UINT8 *Target,
|
IN UINT64 Lun,
|
IN OUT EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET *Packet,
|
IN EFI_EVENT Event OPTIONAL
|
)
|
{
|
SAS_V1_INFO *SasV1Info = SAS_FROM_PASS_THRU(This);
|
struct hisi_hba *hba = SasV1Info->hba;
|
|
return prepare_cmd(hba, Packet);
|
}
|
|
STATIC
|
EFI_STATUS
|
EFIAPI
|
SasV1ExtScsiPassThruGetNextTargetLun (
|
IN EFI_EXT_SCSI_PASS_THRU_PROTOCOL *This,
|
IN OUT UINT8 **Target,
|
IN OUT UINT64 *Lun
|
)
|
{
|
SAS_V1_INFO *SasV1Info = SAS_FROM_PASS_THRU(This);
|
struct hisi_hba *hba = SasV1Info->hba;
|
UINT8 ScsiId[TARGET_MAX_BYTES];
|
UINT8 TargetId;
|
|
if (*Target == NULL || Lun == NULL) {
|
return EFI_INVALID_PARAMETER;
|
}
|
|
SetMem (ScsiId, TARGET_MAX_BYTES, 0xFF);
|
|
TargetId = (*Target)[0];
|
|
if (TargetId == MAX_TARGET_ID) {
|
return EFI_NOT_FOUND;
|
}
|
|
if (CompareMem(*Target, ScsiId, TARGET_MAX_BYTES) == 0) {
|
SetMem (*Target, TARGET_MAX_BYTES,0);
|
} else {
|
(*Target)[0] = (UINT8) (hba->LatestTargetId + 1);
|
}
|
|
*Lun = 0;
|
|
//
|
// Update the LatestTargetId.
|
//
|
hba->LatestTargetId = (*Target)[0];
|
hba->LatestLun = *Lun;
|
|
return EFI_SUCCESS;
|
}
|
|
STATIC
|
EFI_STATUS
|
EFIAPI
|
SasV1ExtScsiPassThruBuildDevicePath (
|
IN EFI_EXT_SCSI_PASS_THRU_PROTOCOL *This,
|
IN UINT8 *Target,
|
IN UINT64 Lun,
|
IN OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath
|
)
|
{
|
SAS_V1_INFO *SasV1Info = SAS_FROM_PASS_THRU(This);
|
|
*DevicePath = DuplicateDevicePath ((EFI_DEVICE_PATH_PROTOCOL *)(SasV1Info->DevicePath));
|
return EFI_SUCCESS;
|
}
|
|
STATIC
|
EFI_STATUS
|
EFIAPI
|
SasV1ExtScsiPassThruGetTargetLun (
|
IN EFI_EXT_SCSI_PASS_THRU_PROTOCOL *This,
|
IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,
|
OUT UINT8 **Target,
|
OUT UINT64 *Lun
|
)
|
{
|
return EFI_UNSUPPORTED;
|
}
|
|
STATIC
|
EFI_STATUS
|
EFIAPI
|
SasV1ExtScsiPassThruResetChannel (
|
IN EFI_EXT_SCSI_PASS_THRU_PROTOCOL *This
|
)
|
{
|
|
return EFI_UNSUPPORTED;
|
}
|
|
STATIC
|
EFI_STATUS
|
EFIAPI
|
SasV1ExtScsiPassThruResetTarget (
|
IN EFI_EXT_SCSI_PASS_THRU_PROTOCOL *This,
|
IN UINT8 *Target,
|
IN UINT64 Lun
|
)
|
{
|
|
return EFI_UNSUPPORTED;
|
}
|
|
STATIC
|
EFI_STATUS
|
EFIAPI
|
SasV1ExtScsiPassThruGetNextTarget (
|
IN EFI_EXT_SCSI_PASS_THRU_PROTOCOL *This,
|
IN OUT UINT8 **Target
|
)
|
{
|
|
return EFI_UNSUPPORTED;
|
}
|
|
STATIC EFI_EXT_SCSI_PASS_THRU_PROTOCOL SasV1ExtScsiPassThruProtocolTemplate = {
|
NULL,
|
SasV1ExtScsiPassThruFunction,
|
SasV1ExtScsiPassThruGetNextTargetLun,
|
SasV1ExtScsiPassThruBuildDevicePath,
|
SasV1ExtScsiPassThruGetTargetLun,
|
SasV1ExtScsiPassThruResetChannel,
|
SasV1ExtScsiPassThruResetTarget,
|
SasV1ExtScsiPassThruGetNextTarget
|
};
|
|
EFI_STATUS
|
EFIAPI
|
SasDriverBindingSupported (
|
IN EFI_DRIVER_BINDING_PROTOCOL *This,
|
IN EFI_HANDLE Controller,
|
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
|
)
|
{
|
PLATFORM_SAS_PROTOCOL *plat;
|
EFI_STATUS Status;
|
|
Status = gBS->OpenProtocol (
|
Controller,
|
&gPlatformSasProtocolGuid,
|
(VOID **) &plat,
|
This->DriverBindingHandle,
|
Controller,
|
EFI_OPEN_PROTOCOL_BY_DRIVER
|
);
|
if (Status == EFI_ALREADY_STARTED) {
|
return EFI_SUCCESS;
|
}
|
if (EFI_ERROR (Status)) {
|
return Status;
|
}
|
|
//
|
// Close the Sas Host used to perform the supported test
|
//
|
gBS->CloseProtocol (
|
Controller,
|
&gPlatformSasProtocolGuid,
|
This->DriverBindingHandle,
|
Controller
|
);
|
|
return EFI_SUCCESS;
|
}
|
|
EFI_STATUS
|
EFIAPI
|
SasDriverBindingStart (
|
IN EFI_DRIVER_BINDING_PROTOCOL *This,
|
IN EFI_HANDLE Controller,
|
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
|
)
|
{
|
EFI_STATUS Status;
|
PLATFORM_SAS_PROTOCOL *plat;
|
SAS_V1_INFO *SasV1Info = NULL;
|
SAS_V1_TRANSPORT_DEVICE_PATH *DevicePath;
|
UINT32 val, base;
|
int i, phy_id = 0;
|
struct hisi_sas_itct *itct;
|
struct hisi_hba *hba;
|
|
Status = gBS->OpenProtocol (
|
Controller,
|
&gPlatformSasProtocolGuid,
|
(VOID **) &plat,
|
This->DriverBindingHandle,
|
Controller,
|
EFI_OPEN_PROTOCOL_BY_DRIVER
|
);
|
|
if (EFI_ERROR (Status)) {
|
if (Status == EFI_ALREADY_STARTED) {
|
return EFI_SUCCESS;
|
}
|
return Status;
|
}
|
|
SasV1Info = AllocateZeroPool (sizeof (SAS_V1_INFO));
|
ASSERT (SasV1Info);
|
SasV1Info->Signature = SAS_DEVICE_SIGNATURE;
|
|
SasV1Info->hba = AllocateZeroPool (sizeof(struct hisi_hba));
|
ASSERT (SasV1Info->hba);
|
hba = SasV1Info->hba;
|
base = hba->base = plat->BaseAddr;
|
|
sas_init(SasV1Info, plat);
|
|
// Wait for sas controller phyup happen
|
MicroSecondDelay(100000);
|
|
for (i = 0; i < PHY_CNT; i++) {
|
val = PHY_READ_REG32(base, CHL_INT2, i);
|
|
if (val & CHL_INT2_SL_PHY_ENA) {
|
phy_id = i;
|
}
|
}
|
|
itct = &hba->itct[0]; //device_id = 0
|
|
hba->port_id = (READ_REG32(base, PHY_PORT_NUM_MA) >> (4 * phy_id)) & 0xf;
|
// Setup itct
|
itct->qw0 = 0x355;
|
itct->sas_addr = PHY_READ_REG32(base, RX_IDAF_DWORD3, phy_id);
|
itct->sas_addr = itct->sas_addr << 32 | PHY_READ_REG32(base, RX_IDAF_DWORD4, phy_id);
|
itct->qw2 = 0;
|
|
// Clear phyup
|
PHY_WRITE_REG32(base, CHL_INT2, phy_id, CHL_INT2_SL_PHY_ENA);
|
val = PHY_READ_REG32(base, CHL_INT0, phy_id);
|
val &= ~CHL_INT0_PHYCTRL_NOTRDY;
|
PHY_WRITE_REG32(base, CHL_INT0, phy_id, val);
|
PHY_WRITE_REG32(base, CHL_INT0_MSK, phy_id, 0x3ce3ee);
|
|
// Need notify
|
val = PHY_READ_REG32(base, SL_CONTROL, phy_id);
|
val |= SL_CONTROL_NOTIFY_EN;
|
PHY_WRITE_REG32(base, SL_CONTROL, phy_id, val);
|
// wait 100ms required for notify takes effect, refer drivers/scsi/hisi_sas/hisi_sas_v1_hw.c
|
MicroSecondDelay(100000);
|
val = PHY_READ_REG32(base, SL_CONTROL, phy_id);
|
val &= ~SL_CONTROL_NOTIFY_EN;
|
PHY_WRITE_REG32(base, SL_CONTROL, phy_id, val);
|
|
CopyMem (&SasV1Info->ExtScsiPassThru, &SasV1ExtScsiPassThruProtocolTemplate, sizeof (EFI_EXT_SCSI_PASS_THRU_PROTOCOL));
|
SasV1Info->ExtScsiPassThruMode.AdapterId = 2;
|
SasV1Info->ExtScsiPassThruMode.Attributes = EFI_EXT_SCSI_PASS_THRU_ATTRIBUTES_PHYSICAL | EFI_EXT_SCSI_PASS_THRU_ATTRIBUTES_LOGICAL;
|
SasV1Info->ExtScsiPassThruMode.IoAlign = 64; //cache line align
|
SasV1Info->ExtScsiPassThru.Mode = &SasV1Info->ExtScsiPassThruMode;
|
|
DevicePath = (SAS_V1_TRANSPORT_DEVICE_PATH *)CreateDeviceNode (
|
HARDWARE_DEVICE_PATH,
|
HW_VENDOR_DP,
|
sizeof (SAS_V1_TRANSPORT_DEVICE_PATH));
|
ASSERT (DevicePath != NULL);
|
SasV1Info->DevicePath = DevicePath;
|
|
CopyMem (&DevicePath->Vendor.Guid, &gPlatformSasProtocolGuid, sizeof (EFI_GUID));
|
DevicePath->PhysBase = base;
|
SetDevicePathNodeLength (&DevicePath->Vendor,
|
sizeof (*DevicePath) - sizeof (DevicePath->End));
|
SetDevicePathEndNode (&DevicePath->End);
|
|
Status = gBS->InstallMultipleProtocolInterfaces (
|
&Controller,
|
&gEfiDevicePathProtocolGuid, DevicePath,
|
&gEfiExtScsiPassThruProtocolGuid, &SasV1Info->ExtScsiPassThru,
|
NULL);
|
ASSERT_EFI_ERROR (Status);
|
|
return EFI_SUCCESS;
|
}
|
|
EFI_STATUS
|
EFIAPI
|
SasDriverBindingStop (
|
IN EFI_DRIVER_BINDING_PROTOCOL *This,
|
IN EFI_HANDLE Controller,
|
IN UINTN NumberOfChildren,
|
IN EFI_HANDLE *ChildHandleBuffer
|
)
|
{
|
SAS_V1_INFO *SasV1Info;
|
EFI_STATUS Status;
|
EFI_EXT_SCSI_PASS_THRU_PROTOCOL *ExtScsi;
|
int i, s;
|
|
Status = gBS->OpenProtocol (
|
Controller,
|
&gEfiExtScsiPassThruProtocolGuid,
|
(VOID **) &ExtScsi,
|
This->DriverBindingHandle,
|
Controller,
|
EFI_OPEN_PROTOCOL_GET_PROTOCOL
|
);
|
if (EFI_ERROR (Status)) {
|
return Status;
|
}
|
|
SasV1Info = SAS_FROM_PASS_THRU(ExtScsi);
|
|
Status = gBS->UninstallMultipleProtocolInterfaces (
|
Controller,
|
&gEfiDevicePathProtocolGuid,
|
SasV1Info->DevicePath,
|
&gEfiExtScsiPassThruProtocolGuid,
|
&SasV1Info->ExtScsiPassThru,
|
NULL);
|
if (!EFI_ERROR (Status)) {
|
gBS->CloseProtocol (
|
Controller,
|
&gPlatformSasProtocolGuid,
|
This->DriverBindingHandle,
|
Controller
|
);
|
|
gBS->CloseEvent (SasV1Info->TimerEvent);
|
|
for (i = 0; i < QUEUE_CNT; i++) {
|
s = sizeof(struct hisi_sas_cmd_hdr) * QUEUE_SLOTS;
|
DmaFreeBuffer(EFI_SIZE_TO_PAGES (s), (VOID *)SasV1Info->hba->cmd_hdr[i]);
|
s = sizeof(struct hisi_sas_complete_hdr) * QUEUE_SLOTS;
|
DmaFreeBuffer(EFI_SIZE_TO_PAGES (s), (VOID *)SasV1Info->hba->complete_hdr[i]);
|
s = sizeof(struct hisi_sas_sts) * QUEUE_SLOTS;
|
DmaFreeBuffer(EFI_SIZE_TO_PAGES (s), (VOID *)SasV1Info->hba->status_buf[i]);
|
s = sizeof(struct hisi_sas_cmd) * QUEUE_SLOTS;
|
DmaFreeBuffer(EFI_SIZE_TO_PAGES (s), (VOID *)SasV1Info->hba->command_table[i]);
|
s = sizeof(struct hisi_sas_sge_page) * QUEUE_SLOTS;
|
DmaFreeBuffer(EFI_SIZE_TO_PAGES (s), (VOID *)SasV1Info->hba->sge[i]);
|
}
|
|
s = SLOT_ENTRIES * sizeof(struct hisi_sas_iost);
|
DmaFreeBuffer(EFI_SIZE_TO_PAGES (s), (VOID *)SasV1Info->hba->iost);
|
s = SLOT_ENTRIES * sizeof(struct hisi_sas_breakpoint);
|
DmaFreeBuffer(EFI_SIZE_TO_PAGES (s), (VOID *)SasV1Info->hba->breakpoint);
|
s = MAX_ITCT_ENTRIES * sizeof(struct hisi_sas_itct);
|
DmaFreeBuffer(EFI_SIZE_TO_PAGES (s), (VOID *)SasV1Info->hba->itct);
|
|
FreePool (SasV1Info->hba->slots);
|
FreePool (SasV1Info->hba);
|
FreePool (SasV1Info);
|
return EFI_SUCCESS;
|
}
|
return Status;
|
}
|
|
EFI_DRIVER_BINDING_PROTOCOL gSasDriverBinding = {
|
SasDriverBindingSupported,
|
SasDriverBindingStart,
|
SasDriverBindingStop,
|
0xa,
|
NULL,
|
NULL
|
};
|
|
EFI_STATUS
|
SasV1Initialize (
|
IN EFI_HANDLE ImageHandle,
|
IN EFI_SYSTEM_TABLE *SystemTable
|
)
|
{
|
return EfiLibInstallDriverBindingComponentName2 (
|
ImageHandle,
|
SystemTable,
|
&gSasDriverBinding,
|
ImageHandle,
|
NULL,
|
NULL
|
);
|
}
|
