/** @file
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*
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* PCI Segment Library for Bcm2711 (RPi4) SoC
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*
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* Copyright (c) 2019, Jeremy Linton
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* Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
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* Copyright (c) 2007 - 2012, Intel Corporation. All rights reserved.<BR>
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*
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* SPDX-License-Identifier: BSD-2-Clause-Patent
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*
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**/
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#include <Base.h>
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#include <Uefi.h>
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#include <Library/BaseLib.h>
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#include <Library/DebugLib.h>
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#include <Library/IoLib.h>
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#include <Library/PcdLib.h>
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#include <Library/PciSegmentLib.h>
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#include <Library/UefiLib.h>
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#include <IndustryStandard/Bcm2711.h>
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#include <IndustryStandard/Pci30.h>
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typedef enum {
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PciCfgWidthUint8 = 0,
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PciCfgWidthUint16,
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PciCfgWidthUint32,
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PciCfgWidthMax
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} PCI_CFG_WIDTH;
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/*
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* This PCIe config space is unusual...
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* The root port is the first bytes of the register space (offset 0)
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* The individual devices are then selected by computing their BDF index
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* and writing that into the CFG_INDEX register (offset 0x9000)
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* the "ECAM" data is then read/writeable at CFG_DATA (offset 0x8000)
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*/
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#define EFI_PCI_ADDR_BUS(bus) ((bus >> 20) & 0xFF) /* Note PCI_SEGMENT_LIB_ADDRESS */
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#define EFI_PCI_ADDR_DEV(dev) ((dev >> 15) & 0x1F)
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#define EFI_PCI_ADDR_FUN(fun) ((fun >> 12) & 0x07)
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/**
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Assert the validity of a PCI Segment address.
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A valid PCI Segment address should not contain 1's in bits 28..31 and 48..63
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@param A The address to validate.
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@param M Additional bits to assert to be zero.
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**/
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#define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A,M) \
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ASSERT (((A) & (0xffff0000f0000000ULL | (M))) == 0)
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/**
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Given the nature of how we access PCI devices, we ensure that
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read/write accesses are serialized through the use of a lock.
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**/
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STATIC
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EFI_LOCK mPciSegmentReadWriteLock = EFI_INITIALIZE_LOCK_VARIABLE (TPL_HIGH_LEVEL);
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STATIC UINT64 mPciSegmentLastAccess; /* Avoid repeat CFG_INDEX updates */
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/**
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Internal worker function to obtain config space base address.
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@param Address The address that encodes the PCI Bus, Device, Function and
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Register.
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@return The value read from the PCI configuration register.
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**/
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STATIC
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UINT64
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PciSegmentLibGetConfigBase (
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IN UINT64 Address
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)
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{
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UINT64 Base;
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UINT64 Offset;
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UINT32 Dev;
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UINT32 Bus;
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UINT32 Data;
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UINT32 HostPortSec;
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Base = PCIE_REG_BASE;
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Offset = Address & 0xFFF; /* Pick off the 4k register offset */
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Address &= 0xFFFFF000; /* Clear the offset leave only the BDF */
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/* The root port is at the base of the PCIe register space */
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if (Address != 0) {
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/* The current device is at CFG_DATA */
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Base += PCIE_EXT_CFG_DATA;
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if (mPciSegmentLastAccess != Address) {
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Dev = EFI_PCI_ADDR_DEV (Address);
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Bus = EFI_PCI_ADDR_BUS (Address);
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HostPortSec = MmioRead8 (PCIE_REG_BASE +
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PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET);
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/*
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* There can only be a single device on bus 1 (downstream of root).
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* Subsequent busses (behind a PCIe switch) can have more.
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*/
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if (Dev > 0 && (Bus <= HostPortSec)) {
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return 0xFFFFFFFF;
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}
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/* Don't probe slots if the link is down */
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Data = MmioRead32 (PCIE_REG_BASE + PCIE_MISC_PCIE_STATUS);
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if ((Data & 0x30) != 0x30) {
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DEBUG ((DEBUG_ERROR, "PCIe link not ready (status=%x)\n", Data));
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return 0xFFFFFFFF;
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}
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MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address);
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mPciSegmentLastAccess = Address;
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}
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}
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return Base + Offset;
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}
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/**
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Internal worker function to read a PCI configuration register.
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@param Address The address that encodes the PCI Bus, Device, Function and
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Register.
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@param Width The width of data to read
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@return The value read from the PCI configuration register.
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**/
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STATIC
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UINT32
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PciSegmentLibReadWorker (
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IN UINT64 Address,
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IN PCI_CFG_WIDTH Width
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)
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{
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UINT64 Base;
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UINT64 Ret;
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EfiAcquireLock (&mPciSegmentReadWriteLock);
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Base = PciSegmentLibGetConfigBase (Address);
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if (Base == 0xFFFFFFFF) {
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EfiReleaseLock (&mPciSegmentReadWriteLock);
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return Base;
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}
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switch (Width) {
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case PciCfgWidthUint8:
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Ret = MmioRead8 (Base);
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break;
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case PciCfgWidthUint16:
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Ret = MmioRead16 (Base);
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break;
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case PciCfgWidthUint32:
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Ret = MmioRead32 (Base);
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break;
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default:
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ASSERT (FALSE);
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Ret = 0;
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}
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EfiReleaseLock (&mPciSegmentReadWriteLock);
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return Ret;
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}
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/**
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Internal worker function to writes a PCI configuration register.
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@param Address The address that encodes the PCI Bus, Device, Function and
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Register.
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@param Width The width of data to write
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@param Data The value to write.
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@return The value written to the PCI configuration register.
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**/
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STATIC
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UINT32
|
PciSegmentLibWriteWorker (
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IN UINT64 Address,
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IN PCI_CFG_WIDTH Width,
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IN UINT32 Data
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)
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{
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UINT64 Base;
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EfiAcquireLock (&mPciSegmentReadWriteLock);
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Base = PciSegmentLibGetConfigBase (Address);
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switch (Width) {
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case PciCfgWidthUint8:
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MmioWrite8 (Base, Data);
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break;
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case PciCfgWidthUint16:
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MmioWrite16 (Base, Data);
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break;
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case PciCfgWidthUint32:
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MmioWrite32 (Base, Data);
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break;
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default:
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ASSERT (FALSE);
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}
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EfiReleaseLock (&mPciSegmentReadWriteLock);
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return Data;
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}
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/**
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Register a PCI device so PCI configuration registers may be accessed after
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SetVirtualAddressMap().
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If any reserved bits in Address are set, then ASSERT().
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@param Address The address that encodes the PCI Bus, Device, Function and
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Register.
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@retval RETURN_SUCCESS The PCI device was registered for runtime access.
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@retval RETURN_UNSUPPORTED An attempt was made to call this function
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after ExitBootServices().
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@retval RETURN_UNSUPPORTED The resources required to access the PCI device
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at runtime could not be mapped.
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@retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
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complete the registration.
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**/
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RETURN_STATUS
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EFIAPI
|
PciSegmentRegisterForRuntimeAccess (
|
IN UINTN Address
|
)
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{
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ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
|
return RETURN_UNSUPPORTED;
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}
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/**
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Reads an 8-bit PCI configuration register.
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Reads and returns the 8-bit PCI configuration register specified by Address.
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This function must guarantee that all PCI read and write operations are serialized.
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If any reserved bits in Address are set, then ASSERT().
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@param Address The address that encodes the PCI Segment, Bus, Device, Function,
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and Register.
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@return The 8-bit PCI configuration register specified by Address.
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**/
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UINT8
|
EFIAPI
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PciSegmentRead8 (
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IN UINT64 Address
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)
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{
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ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
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|
return (UINT8) PciSegmentLibReadWorker (Address, PciCfgWidthUint8);
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}
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/**
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Writes an 8-bit PCI configuration register.
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Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.
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Value is returned. This function must guarantee that all PCI read and write operations are serialized.
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If any reserved bits in Address are set, then ASSERT().
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@param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
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@param Value The value to write.
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@return The value written to the PCI configuration register.
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**/
|
UINT8
|
EFIAPI
|
PciSegmentWrite8 (
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IN UINT64 Address,
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IN UINT8 Value
|
)
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{
|
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
|
|
return (UINT8) PciSegmentLibWriteWorker (Address, PciCfgWidthUint8, Value);
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}
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/**
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Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value.
|
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Reads the 8-bit PCI configuration register specified by Address,
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performs a bitwise OR between the read result and the value specified by OrData,
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and writes the result to the 8-bit PCI configuration register specified by Address.
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The value written to the PCI configuration register is returned.
|
This function must guarantee that all PCI read and write operations are serialized.
|
|
If any reserved bits in Address are set, then ASSERT().
|
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@param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
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@param OrData The value to OR with the PCI configuration register.
|
|
@return The value written to the PCI configuration register.
|
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**/
|
UINT8
|
EFIAPI
|
PciSegmentOr8 (
|
IN UINT64 Address,
|
IN UINT8 OrData
|
)
|
{
|
return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address) | OrData));
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}
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|
/**
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Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value.
|
|
Reads the 8-bit PCI configuration register specified by Address,
|
performs a bitwise AND between the read result and the value specified by AndData,
|
and writes the result to the 8-bit PCI configuration register specified by Address.
|
The value written to the PCI configuration register is returned.
|
This function must guarantee that all PCI read and write operations are serialized.
|
If any reserved bits in Address are set, then ASSERT().
|
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@param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
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@param AndData The value to AND with the PCI configuration register.
|
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@return The value written to the PCI configuration register.
|
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**/
|
UINT8
|
EFIAPI
|
PciSegmentAnd8 (
|
IN UINT64 Address,
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IN UINT8 AndData
|
)
|
{
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return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address) & AndData));
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}
|
|
/**
|
Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,
|
followed a bitwise OR with another 8-bit value.
|
|
Reads the 8-bit PCI configuration register specified by Address,
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performs a bitwise AND between the read result and the value specified by AndData,
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performs a bitwise OR between the result of the AND operation and the value specified by OrData,
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and writes the result to the 8-bit PCI configuration register specified by Address.
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The value written to the PCI configuration register is returned.
|
This function must guarantee that all PCI read and write operations are serialized.
|
|
If any reserved bits in Address are set, then ASSERT().
|
|
@param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
|
@param AndData The value to AND with the PCI configuration register.
|
@param OrData The value to OR with the PCI configuration register.
|
|
@return The value written to the PCI configuration register.
|
|
**/
|
UINT8
|
EFIAPI
|
PciSegmentAndThenOr8 (
|
IN UINT64 Address,
|
IN UINT8 AndData,
|
IN UINT8 OrData
|
)
|
{
|
return PciSegmentWrite8 (Address, (UINT8) ((PciSegmentRead8 (Address) & AndData) | OrData));
|
}
|
|
/**
|
Reads a bit field of a PCI configuration register.
|
|
Reads the bit field in an 8-bit PCI configuration register. The bit field is
|
specified by the StartBit and the EndBit. The value of the bit field is
|
returned.
|
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If any reserved bits in Address are set, then ASSERT().
|
If StartBit is greater than 7, then ASSERT().
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If EndBit is greater than 7, then ASSERT().
|
If EndBit is less than StartBit, then ASSERT().
|
|
@param Address The PCI configuration register to read.
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@param StartBit The ordinal of the least significant bit in the bit field.
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Range 0..7.
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@param EndBit The ordinal of the most significant bit in the bit field.
|
Range 0..7.
|
|
@return The value of the bit field read from the PCI configuration register.
|
|
**/
|
UINT8
|
EFIAPI
|
PciSegmentBitFieldRead8 (
|
IN UINT64 Address,
|
IN UINTN StartBit,
|
IN UINTN EndBit
|
)
|
{
|
return BitFieldRead8 (PciSegmentRead8 (Address), StartBit, EndBit);
|
}
|
|
/**
|
Writes a bit field to a PCI configuration register.
|
|
Writes Value to the bit field of the PCI configuration register. The bit
|
field is specified by the StartBit and the EndBit. All other bits in the
|
destination PCI configuration register are preserved. The new value of the
|
8-bit register is returned.
|
|
If any reserved bits in Address are set, then ASSERT().
|
If StartBit is greater than 7, then ASSERT().
|
If EndBit is greater than 7, then ASSERT().
|
If EndBit is less than StartBit, then ASSERT().
|
If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
@param Address The PCI configuration register to write.
|
@param StartBit The ordinal of the least significant bit in the bit field.
|
Range 0..7.
|
@param EndBit The ordinal of the most significant bit in the bit field.
|
Range 0..7.
|
@param Value The new value of the bit field.
|
|
@return The value written back to the PCI configuration register.
|
|
**/
|
UINT8
|
EFIAPI
|
PciSegmentBitFieldWrite8 (
|
IN UINT64 Address,
|
IN UINTN StartBit,
|
IN UINTN EndBit,
|
IN UINT8 Value
|
)
|
{
|
return PciSegmentWrite8 (
|
Address,
|
BitFieldWrite8 (PciSegmentRead8 (Address), StartBit, EndBit, Value)
|
);
|
}
|
|
/**
|
Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
|
writes the result back to the bit field in the 8-bit port.
|
|
Reads the 8-bit PCI configuration register specified by Address, performs a
|
bitwise OR between the read result and the value specified by
|
OrData, and writes the result to the 8-bit PCI configuration register
|
specified by Address. The value written to the PCI configuration register is
|
returned. This function must guarantee that all PCI read and write operations
|
are serialized. Extra left bits in OrData are stripped.
|
|
If any reserved bits in Address are set, then ASSERT().
|
If StartBit is greater than 7, then ASSERT().
|
If EndBit is greater than 7, then ASSERT().
|
If EndBit is less than StartBit, then ASSERT().
|
If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
@param Address The PCI configuration register to write.
|
@param StartBit The ordinal of the least significant bit in the bit field.
|
Range 0..7.
|
@param EndBit The ordinal of the most significant bit in the bit field.
|
Range 0..7.
|
@param OrData The value to OR with the PCI configuration register.
|
|
@return The value written back to the PCI configuration register.
|
|
**/
|
UINT8
|
EFIAPI
|
PciSegmentBitFieldOr8 (
|
IN UINT64 Address,
|
IN UINTN StartBit,
|
IN UINTN EndBit,
|
IN UINT8 OrData
|
)
|
{
|
return PciSegmentWrite8 (
|
Address,
|
BitFieldOr8 (PciSegmentRead8 (Address), StartBit, EndBit, OrData)
|
);
|
}
|
|
/**
|
Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
|
AND, and writes the result back to the bit field in the 8-bit register.
|
|
Reads the 8-bit PCI configuration register specified by Address, performs a
|
bitwise AND between the read result and the value specified by AndData, and
|
writes the result to the 8-bit PCI configuration register specified by
|
Address. The value written to the PCI configuration register is returned.
|
This function must guarantee that all PCI read and write operations are
|
serialized. Extra left bits in AndData are stripped.
|
|
If any reserved bits in Address are set, then ASSERT().
|
If StartBit is greater than 7, then ASSERT().
|
If EndBit is greater than 7, then ASSERT().
|
If EndBit is less than StartBit, then ASSERT().
|
If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
@param Address The PCI configuration register to write.
|
@param StartBit The ordinal of the least significant bit in the bit field.
|
Range 0..7.
|
@param EndBit The ordinal of the most significant bit in the bit field.
|
Range 0..7.
|
@param AndData The value to AND with the PCI configuration register.
|
|
@return The value written back to the PCI configuration register.
|
|
**/
|
UINT8
|
EFIAPI
|
PciSegmentBitFieldAnd8 (
|
IN UINT64 Address,
|
IN UINTN StartBit,
|
IN UINTN EndBit,
|
IN UINT8 AndData
|
)
|
{
|
return PciSegmentWrite8 (
|
Address,
|
BitFieldAnd8 (PciSegmentRead8 (Address), StartBit, EndBit, AndData)
|
);
|
}
|
|
/**
|
Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
|
bitwise OR, and writes the result back to the bit field in the
|
8-bit port.
|
|
Reads the 8-bit PCI configuration register specified by Address, performs a
|
bitwise AND followed by a bitwise OR between the read result and
|
the value specified by AndData, and writes the result to the 8-bit PCI
|
configuration register specified by Address. The value written to the PCI
|
configuration register is returned. This function must guarantee that all PCI
|
read and write operations are serialized. Extra left bits in both AndData and
|
OrData are stripped.
|
|
If any reserved bits in Address are set, then ASSERT().
|
If StartBit is greater than 7, then ASSERT().
|
If EndBit is greater than 7, then ASSERT().
|
If EndBit is less than StartBit, then ASSERT().
|
If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
@param Address The PCI configuration register to write.
|
@param StartBit The ordinal of the least significant bit in the bit field.
|
Range 0..7.
|
@param EndBit The ordinal of the most significant bit in the bit field.
|
Range 0..7.
|
@param AndData The value to AND with the PCI configuration register.
|
@param OrData The value to OR with the result of the AND operation.
|
|
@return The value written back to the PCI configuration register.
|
|
**/
|
UINT8
|
EFIAPI
|
PciSegmentBitFieldAndThenOr8 (
|
IN UINT64 Address,
|
IN UINTN StartBit,
|
IN UINTN EndBit,
|
IN UINT8 AndData,
|
IN UINT8 OrData
|
)
|
{
|
return PciSegmentWrite8 (
|
Address,
|
BitFieldAndThenOr8 (PciSegmentRead8 (Address), StartBit, EndBit, AndData, OrData)
|
);
|
}
|
|
/**
|
Reads a 16-bit PCI configuration register.
|
|
Reads and returns the 16-bit PCI configuration register specified by Address.
|
This function must guarantee that all PCI read and write operations are serialized.
|
|
If any reserved bits in Address are set, then ASSERT().
|
If Address is not aligned on a 16-bit boundary, then ASSERT().
|
|
@param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
|
|
@return The 16-bit PCI configuration register specified by Address.
|
|
**/
|
UINT16
|
EFIAPI
|
PciSegmentRead16 (
|
IN UINT64 Address
|
)
|
{
|
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);
|
|
return (UINT16) PciSegmentLibReadWorker (Address, PciCfgWidthUint16);
|
}
|
|
/**
|
Writes a 16-bit PCI configuration register.
|
|
Writes the 16-bit PCI configuration register specified by Address with the value specified by Value.
|
Value is returned. This function must guarantee that all PCI read and write operations are serialized.
|
|
If any reserved bits in Address are set, then ASSERT().
|
If Address is not aligned on a 16-bit boundary, then ASSERT().
|
|
@param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
|
@param Value The value to write.
|
|
@return The parameter of Value.
|
|
**/
|
UINT16
|
EFIAPI
|
PciSegmentWrite16 (
|
IN UINT64 Address,
|
IN UINT16 Value
|
)
|
{
|
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);
|
|
return (UINT16) PciSegmentLibWriteWorker (Address, PciCfgWidthUint16, Value);
|
}
|
|
/**
|
Performs a bitwise OR of a 16-bit PCI configuration register with
|
a 16-bit value.
|
|
Reads the 16-bit PCI configuration register specified by Address, performs a
|
bitwise OR between the read result and the value specified by
|
OrData, and writes the result to the 16-bit PCI configuration register
|
specified by Address. The value written to the PCI configuration register is
|
returned. This function must guarantee that all PCI read and write operations
|
are serialized.
|
|
If any reserved bits in Address are set, then ASSERT().
|
If Address is not aligned on a 16-bit boundary, then ASSERT().
|
|
@param Address The address that encodes the PCI Segment, Bus, Device, Function and
|
Register.
|
@param OrData The value to OR with the PCI configuration register.
|
|
@return The value written back to the PCI configuration register.
|
|
**/
|
UINT16
|
EFIAPI
|
PciSegmentOr16 (
|
IN UINT64 Address,
|
IN UINT16 OrData
|
)
|
{
|
return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) | OrData));
|
}
|
|
/**
|
Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value.
|
|
Reads the 16-bit PCI configuration register specified by Address,
|
performs a bitwise AND between the read result and the value specified by AndData,
|
and writes the result to the 16-bit PCI configuration register specified by Address.
|
The value written to the PCI configuration register is returned.
|
This function must guarantee that all PCI read and write operations are serialized.
|
|
If any reserved bits in Address are set, then ASSERT().
|
If Address is not aligned on a 16-bit boundary, then ASSERT().
|
|
@param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
|
@param AndData The value to AND with the PCI configuration register.
|
|
@return The value written to the PCI configuration register.
|
|
**/
|
UINT16
|
EFIAPI
|
PciSegmentAnd16 (
|
IN UINT64 Address,
|
IN UINT16 AndData
|
)
|
{
|
return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) & AndData));
|
}
|
|
/**
|
Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,
|
followed a bitwise OR with another 16-bit value.
|
|
Reads the 16-bit PCI configuration register specified by Address,
|
performs a bitwise AND between the read result and the value specified by AndData,
|
performs a bitwise OR between the result of the AND operation and the value specified by OrData,
|
and writes the result to the 16-bit PCI configuration register specified by Address.
|
The value written to the PCI configuration register is returned.
|
This function must guarantee that all PCI read and write operations are serialized.
|
|
If any reserved bits in Address are set, then ASSERT().
|
If Address is not aligned on a 16-bit boundary, then ASSERT().
|
|
@param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
|
@param AndData The value to AND with the PCI configuration register.
|
@param OrData The value to OR with the PCI configuration register.
|
|
@return The value written to the PCI configuration register.
|
|
**/
|
UINT16
|
EFIAPI
|
PciSegmentAndThenOr16 (
|
IN UINT64 Address,
|
IN UINT16 AndData,
|
IN UINT16 OrData
|
)
|
{
|
return PciSegmentWrite16 (Address, (UINT16) ((PciSegmentRead16 (Address) & AndData) | OrData));
|
}
|
|
/**
|
Reads a bit field of a PCI configuration register.
|
|
Reads the bit field in a 16-bit PCI configuration register. The bit field is
|
specified by the StartBit and the EndBit. The value of the bit field is
|
returned.
|
|
If any reserved bits in Address are set, then ASSERT().
|
If Address is not aligned on a 16-bit boundary, then ASSERT().
|
If StartBit is greater than 15, then ASSERT().
|
If EndBit is greater than 15, then ASSERT().
|
If EndBit is less than StartBit, then ASSERT().
|
|
@param Address The PCI configuration register to read.
|
@param StartBit The ordinal of the least significant bit in the bit field.
|
Range 0..15.
|
@param EndBit The ordinal of the most significant bit in the bit field.
|
Range 0..15.
|
|
@return The value of the bit field read from the PCI configuration register.
|
|
**/
|
UINT16
|
EFIAPI
|
PciSegmentBitFieldRead16 (
|
IN UINT64 Address,
|
IN UINTN StartBit,
|
IN UINTN EndBit
|
)
|
{
|
return BitFieldRead16 (PciSegmentRead16 (Address), StartBit, EndBit);
|
}
|
|
/**
|
Writes a bit field to a PCI configuration register.
|
|
Writes Value to the bit field of the PCI configuration register. The bit
|
field is specified by the StartBit and the EndBit. All other bits in the
|
destination PCI configuration register are preserved. The new value of the
|
16-bit register is returned.
|
|
If any reserved bits in Address are set, then ASSERT().
|
If Address is not aligned on a 16-bit boundary, then ASSERT().
|
If StartBit is greater than 15, then ASSERT().
|
If EndBit is greater than 15, then ASSERT().
|
If EndBit is less than StartBit, then ASSERT().
|
If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
@param Address The PCI configuration register to write.
|
@param StartBit The ordinal of the least significant bit in the bit field.
|
Range 0..15.
|
@param EndBit The ordinal of the most significant bit in the bit field.
|
Range 0..15.
|
@param Value The new value of the bit field.
|
|
@return The value written back to the PCI configuration register.
|
|
**/
|
UINT16
|
EFIAPI
|
PciSegmentBitFieldWrite16 (
|
IN UINT64 Address,
|
IN UINTN StartBit,
|
IN UINTN EndBit,
|
IN UINT16 Value
|
)
|
{
|
return PciSegmentWrite16 (
|
Address,
|
BitFieldWrite16 (PciSegmentRead16 (Address), StartBit, EndBit, Value)
|
);
|
}
|
|
/**
|
Reads the 16-bit PCI configuration register specified by Address,
|
performs a bitwise OR between the read result and the value specified by OrData,
|
and writes the result to the 16-bit PCI configuration register specified by Address.
|
|
If any reserved bits in Address are set, then ASSERT().
|
If Address is not aligned on a 16-bit boundary, then ASSERT().
|
If StartBit is greater than 15, then ASSERT().
|
If EndBit is greater than 15, then ASSERT().
|
If EndBit is less than StartBit, then ASSERT().
|
If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
@param Address The PCI configuration register to write.
|
@param StartBit The ordinal of the least significant bit in the bit field.
|
Range 0..15.
|
@param EndBit The ordinal of the most significant bit in the bit field.
|
Range 0..15.
|
@param OrData The value to OR with the PCI configuration register.
|
|
@return The value written back to the PCI configuration register.
|
|
**/
|
UINT16
|
EFIAPI
|
PciSegmentBitFieldOr16 (
|
IN UINT64 Address,
|
IN UINTN StartBit,
|
IN UINTN EndBit,
|
IN UINT16 OrData
|
)
|
{
|
return PciSegmentWrite16 (
|
Address,
|
BitFieldOr16 (PciSegmentRead16 (Address), StartBit, EndBit, OrData)
|
);
|
}
|
|
/**
|
Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR,
|
and writes the result back to the bit field in the 16-bit port.
|
|
Reads the 16-bit PCI configuration register specified by Address,
|
performs a bitwise OR between the read result and the value specified by OrData,
|
and writes the result to the 16-bit PCI configuration register specified by Address.
|
The value written to the PCI configuration register is returned.
|
This function must guarantee that all PCI read and write operations are serialized.
|
Extra left bits in OrData are stripped.
|
|
If any reserved bits in Address are set, then ASSERT().
|
If Address is not aligned on a 16-bit boundary, then ASSERT().
|
If StartBit is greater than 7, then ASSERT().
|
If EndBit is greater than 7, then ASSERT().
|
If EndBit is less than StartBit, then ASSERT().
|
If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
@param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
|
@param StartBit The ordinal of the least significant bit in the bit field.
|
The ordinal of the least significant bit in a byte is bit 0.
|
@param EndBit The ordinal of the most significant bit in the bit field.
|
The ordinal of the most significant bit in a byte is bit 7.
|
@param AndData The value to AND with the read value from the PCI configuration register.
|
|
@return The value written to the PCI configuration register.
|
|
**/
|
UINT16
|
EFIAPI
|
PciSegmentBitFieldAnd16 (
|
IN UINT64 Address,
|
IN UINTN StartBit,
|
IN UINTN EndBit,
|
IN UINT16 AndData
|
)
|
{
|
return PciSegmentWrite16 (
|
Address,
|
BitFieldAnd16 (PciSegmentRead16 (Address), StartBit, EndBit, AndData)
|
);
|
}
|
|
/**
|
Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
|
bitwise OR, and writes the result back to the bit field in the
|
16-bit port.
|
|
Reads the 16-bit PCI configuration register specified by Address, performs a
|
bitwise AND followed by a bitwise OR between the read result and
|
the value specified by AndData, and writes the result to the 16-bit PCI
|
configuration register specified by Address. The value written to the PCI
|
configuration register is returned. This function must guarantee that all PCI
|
read and write operations are serialized. Extra left bits in both AndData and
|
OrData are stripped.
|
|
If any reserved bits in Address are set, then ASSERT().
|
If StartBit is greater than 15, then ASSERT().
|
If EndBit is greater than 15, then ASSERT().
|
If EndBit is less than StartBit, then ASSERT().
|
If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
@param Address The PCI configuration register to write.
|
@param StartBit The ordinal of the least significant bit in the bit field.
|
Range 0..15.
|
@param EndBit The ordinal of the most significant bit in the bit field.
|
Range 0..15.
|
@param AndData The value to AND with the PCI configuration register.
|
@param OrData The value to OR with the result of the AND operation.
|
|
@return The value written back to the PCI configuration register.
|
|
**/
|
UINT16
|
EFIAPI
|
PciSegmentBitFieldAndThenOr16 (
|
IN UINT64 Address,
|
IN UINTN StartBit,
|
IN UINTN EndBit,
|
IN UINT16 AndData,
|
IN UINT16 OrData
|
)
|
{
|
return PciSegmentWrite16 (
|
Address,
|
BitFieldAndThenOr16 (PciSegmentRead16 (Address), StartBit, EndBit, AndData, OrData)
|
);
|
}
|
|
/**
|
Reads a 32-bit PCI configuration register.
|
|
Reads and returns the 32-bit PCI configuration register specified by Address.
|
This function must guarantee that all PCI read and write operations are serialized.
|
|
If any reserved bits in Address are set, then ASSERT().
|
If Address is not aligned on a 32-bit boundary, then ASSERT().
|
|
@param Address The address that encodes the PCI Segment, Bus, Device, Function,
|
and Register.
|
|
@return The 32-bit PCI configuration register specified by Address.
|
|
**/
|
UINT32
|
EFIAPI
|
PciSegmentRead32 (
|
IN UINT64 Address
|
)
|
{
|
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);
|
|
return PciSegmentLibReadWorker (Address, PciCfgWidthUint32);
|
}
|
|
/**
|
Writes a 32-bit PCI configuration register.
|
|
Writes the 32-bit PCI configuration register specified by Address with the value specified by Value.
|
Value is returned. This function must guarantee that all PCI read and write operations are serialized.
|
|
If any reserved bits in Address are set, then ASSERT().
|
If Address is not aligned on a 32-bit boundary, then ASSERT().
|
|
@param Address The address that encodes the PCI Segment, Bus, Device,
|
Function, and Register.
|
@param Value The value to write.
|
|
@return The parameter of Value.
|
|
**/
|
UINT32
|
EFIAPI
|
PciSegmentWrite32 (
|
IN UINT64 Address,
|
IN UINT32 Value
|
)
|
{
|
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);
|
|
return PciSegmentLibWriteWorker (Address, PciCfgWidthUint32, Value);
|
}
|
|
/**
|
Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit value.
|
|
Reads the 32-bit PCI configuration register specified by Address,
|
performs a bitwise OR between the read result and the value specified by OrData,
|
and writes the result to the 32-bit PCI configuration register specified by Address.
|
The value written to the PCI configuration register is returned.
|
This function must guarantee that all PCI read and write operations are serialized.
|
|
If any reserved bits in Address are set, then ASSERT().
|
If Address is not aligned on a 32-bit boundary, then ASSERT().
|
|
@param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
|
@param OrData The value to OR with the PCI configuration register.
|
|
@return The value written to the PCI configuration register.
|
|
**/
|
UINT32
|
EFIAPI
|
PciSegmentOr32 (
|
IN UINT64 Address,
|
IN UINT32 OrData
|
)
|
{
|
return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) | OrData);
|
}
|
|
/**
|
Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value.
|
|
Reads the 32-bit PCI configuration register specified by Address,
|
performs a bitwise AND between the read result and the value specified by AndData,
|
and writes the result to the 32-bit PCI configuration register specified by Address.
|
The value written to the PCI configuration register is returned.
|
This function must guarantee that all PCI read and write operations are serialized.
|
|
If any reserved bits in Address are set, then ASSERT().
|
If Address is not aligned on a 32-bit boundary, then ASSERT().
|
|
@param Address The address that encodes the PCI Segment, Bus, Device, Function,
|
and Register.
|
@param AndData The value to AND with the PCI configuration register.
|
|
@return The value written to the PCI configuration register.
|
|
**/
|
UINT32
|
EFIAPI
|
PciSegmentAnd32 (
|
IN UINT64 Address,
|
IN UINT32 AndData
|
)
|
{
|
return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) & AndData);
|
}
|
|
/**
|
Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,
|
followed a bitwise OR with another 32-bit value.
|
|
Reads the 32-bit PCI configuration register specified by Address,
|
performs a bitwise AND between the read result and the value specified by AndData,
|
performs a bitwise OR between the result of the AND operation and the value specified by OrData,
|
and writes the result to the 32-bit PCI configuration register specified by Address.
|
The value written to the PCI configuration register is returned.
|
This function must guarantee that all PCI read and write operations are serialized.
|
|
If any reserved bits in Address are set, then ASSERT().
|
If Address is not aligned on a 32-bit boundary, then ASSERT().
|
|
@param Address The address that encodes the PCI Segment, Bus, Device, Function,
|
and Register.
|
@param AndData The value to AND with the PCI configuration register.
|
@param OrData The value to OR with the PCI configuration register.
|
|
@return The value written to the PCI configuration register.
|
|
**/
|
UINT32
|
EFIAPI
|
PciSegmentAndThenOr32 (
|
IN UINT64 Address,
|
IN UINT32 AndData,
|
IN UINT32 OrData
|
)
|
{
|
return PciSegmentWrite32 (Address, (PciSegmentRead32 (Address) & AndData) | OrData);
|
}
|
|
/**
|
Reads a bit field of a PCI configuration register.
|
|
Reads the bit field in a 32-bit PCI configuration register. The bit field is
|
specified by the StartBit and the EndBit. The value of the bit field is
|
returned.
|
|
If any reserved bits in Address are set, then ASSERT().
|
If Address is not aligned on a 32-bit boundary, then ASSERT().
|
If StartBit is greater than 31, then ASSERT().
|
If EndBit is greater than 31, then ASSERT().
|
If EndBit is less than StartBit, then ASSERT().
|
|
@param Address The PCI configuration register to read.
|
@param StartBit The ordinal of the least significant bit in the bit field.
|
Range 0..31.
|
@param EndBit The ordinal of the most significant bit in the bit field.
|
Range 0..31.
|
|
@return The value of the bit field read from the PCI configuration register.
|
|
**/
|
UINT32
|
EFIAPI
|
PciSegmentBitFieldRead32 (
|
IN UINT64 Address,
|
IN UINTN StartBit,
|
IN UINTN EndBit
|
)
|
{
|
return BitFieldRead32 (PciSegmentRead32 (Address), StartBit, EndBit);
|
}
|
|
/**
|
Writes a bit field to a PCI configuration register.
|
|
Writes Value to the bit field of the PCI configuration register. The bit
|
field is specified by the StartBit and the EndBit. All other bits in the
|
destination PCI configuration register are preserved. The new value of the
|
32-bit register is returned.
|
|
If any reserved bits in Address are set, then ASSERT().
|
If Address is not aligned on a 32-bit boundary, then ASSERT().
|
If StartBit is greater than 31, then ASSERT().
|
If EndBit is greater than 31, then ASSERT().
|
If EndBit is less than StartBit, then ASSERT().
|
If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
@param Address The PCI configuration register to write.
|
@param StartBit The ordinal of the least significant bit in the bit field.
|
Range 0..31.
|
@param EndBit The ordinal of the most significant bit in the bit field.
|
Range 0..31.
|
@param Value The new value of the bit field.
|
|
@return The value written back to the PCI configuration register.
|
|
**/
|
UINT32
|
EFIAPI
|
PciSegmentBitFieldWrite32 (
|
IN UINT64 Address,
|
IN UINTN StartBit,
|
IN UINTN EndBit,
|
IN UINT32 Value
|
)
|
{
|
return PciSegmentWrite32 (
|
Address,
|
BitFieldWrite32 (PciSegmentRead32 (Address), StartBit, EndBit, Value)
|
);
|
}
|
|
/**
|
Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
|
writes the result back to the bit field in the 32-bit port.
|
|
Reads the 32-bit PCI configuration register specified by Address, performs a
|
bitwise OR between the read result and the value specified by
|
OrData, and writes the result to the 32-bit PCI configuration register
|
specified by Address. The value written to the PCI configuration register is
|
returned. This function must guarantee that all PCI read and write operations
|
are serialized. Extra left bits in OrData are stripped.
|
|
If any reserved bits in Address are set, then ASSERT().
|
If StartBit is greater than 31, then ASSERT().
|
If EndBit is greater than 31, then ASSERT().
|
If EndBit is less than StartBit, then ASSERT().
|
If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
@param Address The PCI configuration register to write.
|
@param StartBit The ordinal of the least significant bit in the bit field.
|
Range 0..31.
|
@param EndBit The ordinal of the most significant bit in the bit field.
|
Range 0..31.
|
@param OrData The value to OR with the PCI configuration register.
|
|
@return The value written back to the PCI configuration register.
|
|
**/
|
UINT32
|
EFIAPI
|
PciSegmentBitFieldOr32 (
|
IN UINT64 Address,
|
IN UINTN StartBit,
|
IN UINTN EndBit,
|
IN UINT32 OrData
|
)
|
{
|
return PciSegmentWrite32 (
|
Address,
|
BitFieldOr32 (PciSegmentRead32 (Address), StartBit, EndBit, OrData)
|
);
|
}
|
|
/**
|
Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
|
AND, and writes the result back to the bit field in the 32-bit register.
|
|
|
Reads the 32-bit PCI configuration register specified by Address, performs a bitwise
|
AND between the read result and the value specified by AndData, and writes the result
|
to the 32-bit PCI configuration register specified by Address. The value written to
|
the PCI configuration register is returned. This function must guarantee that all PCI
|
read and write operations are serialized. Extra left bits in AndData are stripped.
|
If any reserved bits in Address are set, then ASSERT().
|
If Address is not aligned on a 32-bit boundary, then ASSERT().
|
If StartBit is greater than 31, then ASSERT().
|
If EndBit is greater than 31, then ASSERT().
|
If EndBit is less than StartBit, then ASSERT().
|
If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
@param Address The PCI configuration register to write.
|
@param StartBit The ordinal of the least significant bit in the bit field.
|
Range 0..31.
|
@param EndBit The ordinal of the most significant bit in the bit field.
|
Range 0..31.
|
@param AndData The value to AND with the PCI configuration register.
|
|
@return The value written back to the PCI configuration register.
|
|
**/
|
UINT32
|
EFIAPI
|
PciSegmentBitFieldAnd32 (
|
IN UINT64 Address,
|
IN UINTN StartBit,
|
IN UINTN EndBit,
|
IN UINT32 AndData
|
)
|
{
|
return PciSegmentWrite32 (
|
Address,
|
BitFieldAnd32 (PciSegmentRead32 (Address), StartBit, EndBit, AndData)
|
);
|
}
|
|
/**
|
Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
|
bitwise OR, and writes the result back to the bit field in the
|
32-bit port.
|
|
Reads the 32-bit PCI configuration register specified by Address, performs a
|
bitwise AND followed by a bitwise OR between the read result and
|
the value specified by AndData, and writes the result to the 32-bit PCI
|
configuration register specified by Address. The value written to the PCI
|
configuration register is returned. This function must guarantee that all PCI
|
read and write operations are serialized. Extra left bits in both AndData and
|
OrData are stripped.
|
|
If any reserved bits in Address are set, then ASSERT().
|
If StartBit is greater than 31, then ASSERT().
|
If EndBit is greater than 31, then ASSERT().
|
If EndBit is less than StartBit, then ASSERT().
|
If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
|
|
@param Address The PCI configuration register to write.
|
@param StartBit The ordinal of the least significant bit in the bit field.
|
Range 0..31.
|
@param EndBit The ordinal of the most significant bit in the bit field.
|
Range 0..31.
|
@param AndData The value to AND with the PCI configuration register.
|
@param OrData The value to OR with the result of the AND operation.
|
|
@return The value written back to the PCI configuration register.
|
|
**/
|
UINT32
|
EFIAPI
|
PciSegmentBitFieldAndThenOr32 (
|
IN UINT64 Address,
|
IN UINTN StartBit,
|
IN UINTN EndBit,
|
IN UINT32 AndData,
|
IN UINT32 OrData
|
)
|
{
|
return PciSegmentWrite32 (
|
Address,
|
BitFieldAndThenOr32 (PciSegmentRead32 (Address), StartBit, EndBit, AndData, OrData)
|
);
|
}
|
|
/**
|
Reads a range of PCI configuration registers into a caller supplied buffer.
|
|
Reads the range of PCI configuration registers specified by StartAddress and
|
Size into the buffer specified by Buffer. This function only allows the PCI
|
configuration registers from a single PCI function to be read. Size is
|
returned. When possible 32-bit PCI configuration read cycles are used to read
|
from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
|
and 16-bit PCI configuration read cycles may be used at the beginning and the
|
end of the range.
|
|
If any reserved bits in StartAddress are set, then ASSERT().
|
If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
|
If Size > 0 and Buffer is NULL, then ASSERT().
|
|
@param StartAddress The starting address that encodes the PCI Segment, Bus,
|
Device, Function and Register.
|
@param Size The size in bytes of the transfer.
|
@param Buffer The pointer to a buffer receiving the data read.
|
|
@return Size
|
|
**/
|
UINTN
|
EFIAPI
|
PciSegmentReadBuffer (
|
IN UINT64 StartAddress,
|
IN UINTN Size,
|
OUT VOID *Buffer
|
)
|
{
|
UINTN ReturnValue;
|
|
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);
|
ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
|
|
if (Size == 0) {
|
return Size;
|
}
|
|
ASSERT (Buffer != NULL);
|
|
//
|
// Save Size for return
|
//
|
ReturnValue = Size;
|
|
if ((StartAddress & BIT0) != 0) {
|
//
|
// Read a byte if StartAddress is byte aligned
|
//
|
*(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress);
|
StartAddress += sizeof (UINT8);
|
Size -= sizeof (UINT8);
|
Buffer = (UINT8*)Buffer + 1;
|
}
|
|
if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {
|
//
|
// Read a word if StartAddress is word aligned
|
//
|
WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress));
|
StartAddress += sizeof (UINT16);
|
Size -= sizeof (UINT16);
|
Buffer = (UINT16*)Buffer + 1;
|
}
|
|
while (Size >= sizeof (UINT32)) {
|
//
|
// Read as many double words as possible
|
//
|
WriteUnaligned32 (Buffer, PciSegmentRead32 (StartAddress));
|
StartAddress += sizeof (UINT32);
|
Size -= sizeof (UINT32);
|
Buffer = (UINT32*)Buffer + 1;
|
}
|
|
if (Size >= sizeof (UINT16)) {
|
//
|
// Read the last remaining word if exist
|
//
|
WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress));
|
StartAddress += sizeof (UINT16);
|
Size -= sizeof (UINT16);
|
Buffer = (UINT16*)Buffer + 1;
|
}
|
|
if (Size >= sizeof (UINT8)) {
|
//
|
// Read the last remaining byte if exist
|
//
|
*(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress);
|
}
|
|
return ReturnValue;
|
}
|
|
|
/**
|
Copies the data in a caller supplied buffer to a specified range of PCI
|
configuration space.
|
|
Writes the range of PCI configuration registers specified by StartAddress and
|
Size from the buffer specified by Buffer. This function only allows the PCI
|
configuration registers from a single PCI function to be written. Size is
|
returned. When possible 32-bit PCI configuration write cycles are used to
|
write from StartAdress to StartAddress + Size. Due to alignment restrictions,
|
8-bit and 16-bit PCI configuration write cycles may be used at the beginning
|
and the end of the range.
|
|
If any reserved bits in StartAddress are set, then ASSERT().
|
If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
|
If Size > 0 and Buffer is NULL, then ASSERT().
|
|
@param StartAddress The starting address that encodes the PCI Segment, Bus,
|
Device, Function and Register.
|
@param Size The size in bytes of the transfer.
|
@param Buffer The pointer to a buffer containing the data to write.
|
|
@return The parameter of Size.
|
|
**/
|
UINTN
|
EFIAPI
|
PciSegmentWriteBuffer (
|
IN UINT64 StartAddress,
|
IN UINTN Size,
|
IN VOID *Buffer
|
)
|
{
|
UINTN ReturnValue;
|
|
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);
|
ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
|
|
if (Size == 0) {
|
return 0;
|
}
|
|
ASSERT (Buffer != NULL);
|
|
// The Bcm/Rpi has a single cfg which can be mapped
|
// to any given device on the bus, which means we need to remap
|
// it basically everytime a new config access is done
|
|
//
|
// Save Size for return
|
//
|
ReturnValue = Size;
|
|
if ((StartAddress & BIT0) != 0) {
|
//
|
// Write a byte if StartAddress is byte aligned
|
//
|
PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer);
|
StartAddress += sizeof (UINT8);
|
Size -= sizeof (UINT8);
|
Buffer = (UINT8*)Buffer + 1;
|
}
|
|
if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {
|
//
|
// Write a word if StartAddress is word aligned
|
//
|
PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer));
|
StartAddress += sizeof (UINT16);
|
Size -= sizeof (UINT16);
|
Buffer = (UINT16*)Buffer + 1;
|
}
|
|
while (Size >= sizeof (UINT32)) {
|
//
|
// Write as many double words as possible
|
//
|
PciSegmentWrite32 (StartAddress, ReadUnaligned32 (Buffer));
|
StartAddress += sizeof (UINT32);
|
Size -= sizeof (UINT32);
|
Buffer = (UINT32*)Buffer + 1;
|
}
|
|
if (Size >= sizeof (UINT16)) {
|
//
|
// Write the last remaining word if exist
|
//
|
PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer));
|
StartAddress += sizeof (UINT16);
|
Size -= sizeof (UINT16);
|
Buffer = (UINT16*)Buffer + 1;
|
}
|
|
if (Size >= sizeof (UINT8)) {
|
//
|
// Write the last remaining byte if exist
|
//
|
PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer);
|
}
|
|
return ReturnValue;
|
}
|
