/** @file
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*
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* PCI Host Bridge Library instance for Bcm2711 ARM SOC
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*
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* Copyright (c) 2019, Jeremy Linton
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* Copyright (c) 2017, Linaro Ltd. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-2-Clause-Patent
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*
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* This module initializes the Pci as close to a standard
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* PCI root complex as possible. The general information
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* for this driver was sourced from.
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*
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* See https://github.com/raspberrypi/linux/blob/rpi-5.3.y/drivers/pci/controller/pcie-brcmstb.c
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* and https://github.com/raspberrypi/linux/blob/rpi-5.3.y/arch/arm/boot/dts/bcm2838.dtsi
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*
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**/
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#include <IndustryStandard/Bcm2711.h>
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#include <IndustryStandard/Pci22.h>
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#include <Library/ArmLib.h>
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#include <Library/DebugLib.h>
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#include <Library/IoLib.h>
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#include <Library/PcdLib.h>
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#include <Library/PciHostBridgeLib.h>
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#include <Library/UefiBootServicesTableLib.h>
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#include <PiDxe.h>
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#include <Protocol/PciHostBridgeResourceAllocation.h>
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STATIC
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UINT32
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RdRegister (
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UINT32 Offset
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)
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{
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ArmDataMemoryBarrier ();
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return MmioRead32 (PCIE_REG_BASE + Offset);
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}
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STATIC
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VOID
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RMWRegister (
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UINT32 Offset,
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UINT32 Mask,
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UINT32 In
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)
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{
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EFI_PHYSICAL_ADDRESS Addr;
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UINT32 Data;
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UINT32 Shift;
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Addr = PCIE_REG_BASE + Offset;
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Shift = 1;
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if (In) {
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while (!(Mask & Shift))
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Shift <<= 1;
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Data = (MmioRead32 (Addr) & ~Mask) | ((In * Shift) & Mask);
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} else {
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Data = MmioRead32 (Addr) & ~Mask;
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}
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MmioWrite32 (Addr, Data);
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ArmDataMemoryBarrier ();
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}
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STATIC
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VOID
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WdRegister (
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UINT32 Offset,
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UINT32 In
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)
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{
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MmioWrite32 (PCIE_REG_BASE + Offset, In);
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ArmDataMemoryBarrier ();
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}
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EFI_STATUS
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EFIAPI
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Bcm2711PciHostBridgeLibConstructor (
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IN EFI_HANDLE ImageHandle,
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IN EFI_SYSTEM_TABLE *SystemTable
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)
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{
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INTN Timeout;
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UINT32 Data;
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EFI_PHYSICAL_ADDRESS TopOfPciMap;
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DEBUG ((DEBUG_VERBOSE, "PCIe RootBridge constructor\n"));
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Timeout = 100;
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// Reset controller
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RMWRegister (PCIE_RGR1_SW_INIT_1, PCIE_RGR1_SW_INIT_1_INIT_MASK, 1);
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// PERST
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RMWRegister (PCIE_RGR1_SW_INIT_1, PCIE_RGR1_SW_INIT_1_PERST_MASK, 1);
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gBS->Stall (1000);
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// take the bridge out of reset
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RMWRegister (PCIE_RGR1_SW_INIT_1, PCIE_RGR1_SW_INIT_1_INIT_MASK, 0);
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RMWRegister (PCIE_MISC_HARD_PCIE_HARD_DEBUG,
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PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK, 0);
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RdRegister (PCIE_MISC_HARD_PCIE_HARD_DEBUG);
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// Wait for SerDes to be stable
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gBS->Stall (1000);
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// Read revision
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Data = RdRegister (PCIE_MISC_REVISION);
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DEBUG ((DEBUG_INFO, "RootBridge: Revision %x\n", Data & PCIE_MISC_REVISION_MAJMIN_MASK));
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RMWRegister (PCIE_MISC_MISC_CTRL, PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK, 1);
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RMWRegister (PCIE_MISC_MISC_CTRL, PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK, 1);
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RMWRegister (PCIE_MISC_MISC_CTRL, PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK, BURST_SIZE_128);
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//
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// "RC_BAR2" is the inbound TLP window.
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// Having non RAM regions in the window is ok (and encouraged? for PtP?)
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// so lets just map the entire address space.
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//
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// For regions > 64K then the pci->mem window size = log2(size)-15
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// which is dumped into the low bits of the offset and written to
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// the "LO" register with the high bits of the offset written into
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// the "HI" part. The Linux driver makes the point that the offset
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// must be aligned to its size aka a 1G region must start on a 1G
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// boundary. The size parms are 1GB=0xf=log2(size)-15), or 4G=0x11
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//
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DEBUG ((DEBUG_VERBOSE, "RootBridge: Program bottom 4G of ram\n"));
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// lets assume a start addr of 0, size 4G
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WdRegister (PCIE_MISC_RC_BAR2_CONFIG_LO, 0x11); /* Size = 4G */
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WdRegister (PCIE_MISC_RC_BAR2_CONFIG_HI, 0); /* Start at addr0 */
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RMWRegister (PCIE_MISC_MISC_CTRL, PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK, 0x11);
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// RC_BAR1 pcie->gisb disable
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WdRegister (PCIE_MISC_RC_BAR1_CONFIG_LO, 0);
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// RC_BAR3 pcie->scb disable
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WdRegister (PCIE_MISC_RC_BAR3_CONFIG_LO, 0);
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TopOfPciMap = PCIE_TOP_OF_MEM_WIN;
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DEBUG ((DEBUG_VERBOSE, "RootBridge: MMIO PCIe addr %llx\n", TopOfPciMap));
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//
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// Setup the PCI side of the MMIO window.
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//
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// All the _WIN0_ values make one think there can be more than one
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// mapping, which might mean it's possible to program a prefetchable
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// window, or a PIO window...
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//
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WdRegister (PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO, TopOfPciMap);
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WdRegister (PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI, TopOfPciMap >> 32);
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//
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// Set up the CPU MMIO addresses. The BASE_LIMIT register holds the
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// bottom part of the start and end addresses in a 16-bit field (64k)
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// aligned on a 1M boundary (aka only 12 bit active) the top 32-bits
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// are then in their own registers. Further these address ranges are
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// setup to match the Linux driver and seem less than ideal on the RPi
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//
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// The mapping should be 1:1 if possible
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//
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EFI_PHYSICAL_ADDRESS CpuAddrStart = PCIE_CPU_MMIO_WINDOW;
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EFI_PHYSICAL_ADDRESS CpuAddrEnd = CpuAddrStart + PCIE_BRIDGE_MMIO_LEN;
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DEBUG ((DEBUG_VERBOSE, "RootBridge: MMIO CPU addr %llx\n", CpuAddrStart));
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RMWRegister (PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT,
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PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK, CpuAddrStart >> 20);
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RMWRegister (PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT,
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PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK, CpuAddrEnd >> 20);
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RMWRegister (PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI,
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PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK, CpuAddrStart >> 32);
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RMWRegister (PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI,
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PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK, CpuAddrEnd >> 32);
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//
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// Consider MSI setup here, not that it matters much its likely the legacy intX
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// is as fast or faster...
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//
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// Clear and mask interrupts.
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WdRegister (PCIE_INTR2_CPU_MASK_CLR, 0xffffffff);
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WdRegister (PCIE_INTR2_CPU_MASK_SET, 0xffffffff);
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// Set link cap & link ctl?
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//RMWRegister (BRCM_PCIE_CAP_REGS+PCI_LNKCAP, LNKCAP, pen);
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//RMWRegister (BRCM_PCIE_CTL_REGS+PCI_LNKCAP, LNKCAP, pen);
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// De-assert PERST
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RMWRegister (PCIE_RGR1_SW_INIT_1, PCIE_RGR1_SW_INIT_1_PERST_MASK, 0);
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DEBUG ((DEBUG_VERBOSE, "RootBridge: Reset done\n"));
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// Wait for linkup
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do {
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Data = RdRegister (PCIE_MISC_PCIE_STATUS);
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gBS->Stall (1000);
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Timeout --;
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} while (((Data & 0x30) != 0x030) && (Timeout));
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DEBUG ((DEBUG_VERBOSE, "PCIe link ready (status=%x) Timeout=%d\n", Data, Timeout));
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if ((Data & 0x80) != 0x80) {
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DEBUG ((DEBUG_ERROR, "PCIe link not in RC mode (status=%x)\n", Data));
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return EFI_UNSUPPORTED;
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}
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// Change class code of the root port
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RMWRegister(BRCM_PCIE_CLASS, PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK, 0x60400);
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//
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// PCIe->SCB endian mode for BAR
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// field ENDIAN_MODE_BAR2 = little endian = 0
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//
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RMWRegister (PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1,
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PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK, 0);
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RMWRegister (PCIE_MISC_HARD_PCIE_HARD_DEBUG,
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PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK, 1);
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return EFI_SUCCESS;
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}
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