/** @file
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*
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* PCI Host Bridge Library instance for Bcm2711 ARM SOC
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*
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* Copyright (c) 2019, Jeremy Linton
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* Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
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*
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* SPDX-License-Identifier: BSD-2-Clause-Patent
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*
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**/
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#include <IndustryStandard/Bcm2711.h>
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#include <IndustryStandard/Pci22.h>
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#include <Library/DebugLib.h>
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#include <Library/DevicePathLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/PcdLib.h>
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#include <Library/PciHostBridgeLib.h>
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#include <PiDxe.h>
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#include <Protocol/PciRootBridgeIo.h>
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#include <Protocol/PciHostBridgeResourceAllocation.h>
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#pragma pack(1)
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typedef PACKED struct {
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ACPI_HID_DEVICE_PATH AcpiDevicePath;
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EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
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} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;
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#pragma pack ()
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STATIC CONST EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[] = {
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{
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{
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{
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ACPI_DEVICE_PATH,
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ACPI_DP,
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{
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(UINT8)(sizeof (ACPI_HID_DEVICE_PATH)),
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(UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
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}
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},
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EISA_PNP_ID (0x0A08), // PCI Express
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0
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},
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{
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END_DEVICE_PATH_TYPE,
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END_ENTIRE_DEVICE_PATH_SUBTYPE,
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{
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END_DEVICE_PATH_LENGTH,
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0
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}
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}
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},
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};
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GLOBAL_REMOVE_IF_UNREFERENCED
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CHAR16 *mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = {
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L"Mem", L"I/O", L"Bus"
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};
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// These should come from the PCD...
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#define BCM2711_PCI_SEG0_BUSNUM_MIN 0x00
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#define BCM2711_PCI_SEG0_BUSNUM_MAX 0xFF
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#define BCM2711_PCI_SEG0_PORTIO_MIN 0x01
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#define BCM2711_PCI_SEG0_PORTIO_MAX 0x00 // MIN>MAX disables PIO
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#define BCM2711_PCI_SEG0_PORTIO_OFFSET 0x00
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// The bridge thinks its MMIO is here (which means it can't access this area in phy ram)
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#define BCM2711_PCI_SEG0_MMIO32_MIN PCIE_TOP_OF_MEM_WIN
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#define BCM2711_PCI_SEG0_MMIO32_MAX (PCIE_TOP_OF_MEM_WIN + PCIE_BRIDGE_MMIO_LEN)
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// The CPU views it via a window here..
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#define BCM2711_PCI_SEG0_MMIO32_XLATE (PCIE_CPU_MMIO_WINDOW - PCIE_TOP_OF_MEM_WIN)
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// We might be able to size another region?
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#define BCM2711_PCI_SEG0_MMIO64_MIN 0x00
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#define BCM2711_PCI_SEG0_MMIO64_MAX 0x00
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//
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// See description in MdeModulePkg/Include/Library/PciHostBridgeLib.h
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//
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PCI_ROOT_BRIDGE mPciRootBridges[] = {
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{
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0, // Segment
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0, // Supports
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0, // Attributes
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FALSE, // DmaAbove4G
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FALSE, // NoExtendedConfigSpace (true=256 byte config, false=4k)
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FALSE, // ResourceAssigned
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EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM, // AllocationAttributes
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{ BCM2711_PCI_SEG0_BUSNUM_MIN,
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BCM2711_PCI_SEG0_BUSNUM_MAX }, // Bus
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{ BCM2711_PCI_SEG0_PORTIO_MIN,
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BCM2711_PCI_SEG0_PORTIO_MAX,
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MAX_UINT64 - BCM2711_PCI_SEG0_PORTIO_OFFSET + 1 }, // Io
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{ BCM2711_PCI_SEG0_MMIO32_MIN,
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BCM2711_PCI_SEG0_MMIO32_MAX,
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MAX_UINT64 - BCM2711_PCI_SEG0_MMIO32_XLATE + 1 }, // Mem
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{ MAX_UINT64, 0x0 }, // MemAbove4G
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{ MAX_UINT64, 0x0 }, // Pefetchable Mem
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{ MAX_UINT64, 0x0 }, // Pefetchable MemAbove4G
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(EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[0]
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}
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};
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/**
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Return all the root bridge instances in an array.
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@param Count Return the count of root bridge instances.
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@return All the root bridge instances in an array.
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The array should be passed into PciHostBridgeFreeRootBridges()
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when it's not used.
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**/
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PCI_ROOT_BRIDGE *
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EFIAPI
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PciHostBridgeGetRootBridges (
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OUT UINTN *Count
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)
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{
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*Count = ARRAY_SIZE (mPciRootBridges);
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return mPciRootBridges;
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}
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/**
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Free the root bridge instances array returned from PciHostBridgeGetRootBridges().
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@param Bridges The root bridge instances array.
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@param Count The count of the array.
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**/
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VOID
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EFIAPI
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PciHostBridgeFreeRootBridges (
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PCI_ROOT_BRIDGE *Bridges,
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UINTN Count
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)
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{
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}
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/**
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Inform the platform that the resource conflict happens.
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@param HostBridgeHandle Handle of the Host Bridge.
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@param Configuration Pointer to PCI I/O and PCI memory resource
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descriptors. The Configuration contains the resources
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for all the root bridges. The resource for each root
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bridge is terminated with END descriptor and an
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additional END is appended indicating the end of the
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entire resources. The resource descriptor field
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values follow the description in
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EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
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.SubmitResources().
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**/
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VOID
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EFIAPI
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PciHostBridgeResourceConflict (
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EFI_HANDLE HostBridgeHandle,
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VOID *Configuration
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)
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{
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EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
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UINTN RootBridgeIndex;
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DEBUG ((DEBUG_ERROR, "PciHostBridge: Resource conflict happens!\n"));
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RootBridgeIndex = 0;
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Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;
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while (Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) {
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DEBUG ((DEBUG_ERROR, "RootBridge[%d]:\n", RootBridgeIndex++));
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for (; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) {
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ASSERT (Descriptor->ResType <
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ARRAY_SIZE (mPciHostBridgeLibAcpiAddressSpaceTypeStr));
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DEBUG ((DEBUG_ERROR, " %s: Length/Alignment = 0x%lx / 0x%lx\n",
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mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType],
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Descriptor->AddrLen, Descriptor->AddrRangeMax
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));
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if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) {
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DEBUG ((DEBUG_ERROR, " Granularity/SpecificFlag = %ld / %02x%s\n",
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Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag,
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((Descriptor->SpecificFlag &
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EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE
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) != 0) ? L" (Prefetchable)" : L""
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));
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}
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}
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//
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// Skip the END descriptor for root bridge
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//
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ASSERT (Descriptor->Desc == ACPI_END_TAG_DESCRIPTOR);
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Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)(
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(EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1
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);
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}
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}
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