/** @file
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*
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* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
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* Copyright (c) 2015, Linaro Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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* which accompanies this distribution. The full text of the license may be found at
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* http://opensource.org/licenses/bsd-license.php
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*
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* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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*
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**/
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#ifndef _PLATFORM_SYS_CTRL_LIB_H_
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#define _PLATFORM_SYS_CTRL_LIB_H_
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#define PACKAGE_16CORE 0
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#define PACKAGE_32CORE 1
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#define PACKAGE_RESERVED 2
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#define PACKAGE_TYPE_NUM 3
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UINT32 PlatformGetPackageType (VOID);
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VOID DisplayCpuInfo (VOID);
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UINT32 CheckChipIsEc(VOID);
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UINTN PlatformGetPll (UINT32 NodeId, UINTN Pll);
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#define DJTAG_READ_INVALID_VALUE 0xFFFFFFFF
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#define DJTAG_CHAIN_ID_AA 1
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#define DJTAG_CHAIN_ID_LLC 4
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#define SC_DJTAG_MSTR_EN_OFFSET 0x6800
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#define SC_DJTAG_MSTR_START_EN_OFFSET 0x6804
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#define SC_DJTAG_SEC_ACC_EN_OFFSET 0x6808
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#define SC_DJTAG_DEBUG_MODULE_SEL_OFFSET 0x680C
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#define SC_DJTAG_MSTR_WR_OFFSET 0x6810
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#define SC_DJTAG_CHAIN_UNIT_CFG_EN_OFFSET 0x6814
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#define SC_DJTAG_MSTR_ADDR_OFFSET 0x6818
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#define SC_DJTAG_MSTR_DATA_OFFSET 0x681C
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#define SC_DJTAG_TMOUT_OFFSET 0x6820
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#define SC_TDRE_OP_ADDR_OFFSET 0x6824
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#define SC_TDRE_WDATA_OFFSET 0x6828
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#define SC_TDRE_REPAIR_EN_OFFSET 0x682C
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#define SC_DJTAG_RD_DATA0_OFFSET 0xE800
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#define SC_TDRE_RDATA0_OFFSET 0xE830
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UINTN PlatformGetI2cBase(UINT32 Socket,UINT8 Port);
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VOID PlatformAddressMapCleanUp (VOID);
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VOID PlatformDisableDdrWindow (VOID);
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VOID PlatformEnableArchTimer (VOID);
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EFI_STATUS
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DawFindFreeWindow (UINTN Socket, UINTN *DawIndex);
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VOID DawSetWindow (UINTN Socket, UINTN WindowIndex, UINT32 Value);
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VOID DJTAG_TDRE_WRITE(UINT32 Offset, UINT32 Value, UINT32 ChainID, UINT32 NodeId, BOOLEAN Repair);
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UINT32 DJTAG_TDRE_READ(UINT32 Offset, UINT32 ChainID, UINT32 NodeId, BOOLEAN Repair);
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VOID RemoveRoceReset(VOID);
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UINTN PlatformGetDdrChannel (VOID);
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VOID ITSCONFIG (VOID);
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VOID MN_CONFIG (VOID);
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VOID SmmuConfigForOS (VOID);
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VOID SmmuConfigForBios (VOID);
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VOID StartUpBSP (VOID);
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VOID LlcCleanInvalidate (VOID);
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UINTN PlatformGetCpuFreq (UINT8 Socket);
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VOID ClearInterruptStatus(VOID);
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UINTN PlatformGetCoreCount (VOID);
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VOID DAWConfigEn(UINT32 socket);
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VOID DResetUsb ();
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UINT32 PlatformGetEhciBase ();
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UINT32 PlatformGetOhciBase ();
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VOID PlatformPllInit();
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// PLL initialization for super IO clusters.
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VOID SiclPllInit(UINT32 SclId);
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VOID PlatformDeviceDReset();
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VOID PlatformGicdInit();
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VOID PlatformLpcInit();
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// Synchronize architecture timer counter between different super computing
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// clusters.
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VOID PlatformArchTimerSynchronize(VOID);
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VOID PlatformEventBroadcastConfig(VOID);
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UINTN GetDjtagRegBase(UINT32 NodeId);
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VOID LlcCleanInvalidateAsm(VOID);
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VOID PlatformMdioInit(VOID);
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VOID DisableClusterClock(UINTN CpuClusterBase);
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VOID EnableClusterClock(UINTN CpuClusterBase);
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VOID DisableSocketClock (UINT8 Skt);
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EFI_STATUS EFIAPI HandleI2CException (UINT32 Socket, UINT32 Port);
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EFI_STATUS EFIAPI HandleI2CExceptionBySocket (UINT32 Socket);
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#endif
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