/** @file
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*
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* Copyright (c) 2016, Hisilicon Limited. All rights reserved.
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* Copyright (c) 2016, Linaro Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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* which accompanies this distribution. The full text of the license may be found at
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* http://opensource.org/licenses/bsd-license.php
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*
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* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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*
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**/
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#ifndef _LPC_LIB_H_
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#define _LPC_LIB_H_
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#include <Uefi.h>
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#define PCIE_SUBSYS_IO_MUX 0xA0170000
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#define PCIE_SUBSYS_IOMG033 (PCIE_SUBSYS_IO_MUX + 0x84)
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#define PCIE_SUBSYS_IOMG035 (PCIE_SUBSYS_IO_MUX + 0x8C)
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#define PCIE_SUBSYS_IOMG036 (PCIE_SUBSYS_IO_MUX + 0x90)
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#define PCIE_SUBSYS_IOMG045 (PCIE_SUBSYS_IO_MUX + 0xB4)
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#define PCIE_SUBSYS_IOMG046 (PCIE_SUBSYS_IO_MUX + 0xB8)
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#define PCIE_SUBSYS_IOMG047 (PCIE_SUBSYS_IO_MUX + 0xBC)
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#define PCIE_SUBSYS_IOMG048 (PCIE_SUBSYS_IO_MUX + 0xC0)
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#define PCIE_SUBSYS_IOMG049 (PCIE_SUBSYS_IO_MUX + 0xC4)
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#define PCIE_SUBSYS_IOMG050 (PCIE_SUBSYS_IO_MUX + 0xC8)
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#define IO_WRAP_CTRL_BASE 0xA0100000
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#define SC_LPC_CLK_EN_REG (IO_WRAP_CTRL_BASE + 0x03a0)
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#define SC_LPC_CLK_DIS_REG (IO_WRAP_CTRL_BASE + 0x03a4)
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#define SC_LPC_BUS_CLK_EN_REG (IO_WRAP_CTRL_BASE + 0x03a8)
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#define SC_LPC_BUS_CLK_DIS_REG (IO_WRAP_CTRL_BASE + 0x03ac)
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#define SC_LPC_RESET_REQ (IO_WRAP_CTRL_BASE + 0x0ad8)
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#define SC_LPC_RESET_DREQ (IO_WRAP_CTRL_BASE + 0x0adc)
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#define SC_LPC_BUS_RESET_REQ (IO_WRAP_CTRL_BASE + 0x0ae0)
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#define SC_LPC_BUS_RESET_DREQ (IO_WRAP_CTRL_BASE + 0x0ae4)
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#define SC_LPC_CTRL_REG (IO_WRAP_CTRL_BASE + 0x2028)
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#define LPC_BASE 0xA01B0000
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#define LPC_START_REG (LPC_BASE + 0x00)
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#define LPC_OP_STATUS_REG (LPC_BASE + 0x04)
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#define LPC_IRQ_ST_REG (LPC_BASE + 0x08)
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#define LPC_OP_LEN_REG (LPC_BASE + 0x10)
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#define LPC_CMD_REG (LPC_BASE + 0x14)
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#define LPC_FWH_ID_MSIZE_REG (LPC_BASE + 0x18)
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#define LPC_ADDR_REG (LPC_BASE + 0x20)
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#define LPC_WDATA_REG (LPC_BASE + 0x24)
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#define LPC_RDATA_REG (LPC_BASE + 0x28)
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#define LPC_LONG_CNT_REG (LPC_BASE + 0x30)
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#define LPC_TX_FIFO_ST_REG (LPC_BASE + 0x50)
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#define LPC_RX_FIFO_ST_REG (LPC_BASE + 0x54)
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#define LPC_TIME_OUT_REG (LPC_BASE + 0x58)
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#define LPC_SIRQ_CTRL0_REG (LPC_BASE + 0x80)
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#define LPC_SIRQ_CTRL1_REG (LPC_BASE + 0x84)
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#define LPC_SIRQ_INT_REG (LPC_BASE + 0x90)
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#define LPC_SIRQ_INT_MASK_REG (LPC_BASE + 0x94)
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#define LPC_SIRQ_STAT_REG (LPC_BASE + 0xA0)
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#define LPC_FIFO_LEN (16)
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typedef enum{
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LPC_ADDR_MODE_INCREASE,
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LPC_ADDR_MODE_SINGLE
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}LPC_ADDR_MODE;
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typedef enum{
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LPC_TYPE_IO,
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LPC_TYPE_MEM,
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LPC_TYPE_FWH
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}LPC_TYPE;
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typedef union {
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struct{
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UINT32 lpc_wr:1;
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UINT32 lpc_type:2;
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UINT32 same_addr:1;
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UINT32 resv:28;
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}bits;
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UINT32 u32;
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}LPC_CMD_STRUCT;
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typedef union {
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struct{
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UINT32 op_len:5;
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UINT32 resv:27;
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}bits;
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UINT32 u32;
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}LPC_OP_LEN_STRUCT;
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VOID LpcInit(VOID);
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BOOLEAN LpcIdle(VOID);
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EFI_STATUS LpcByteWrite(
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IN UINT32 Addr,
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IN UINT8 Data);
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EFI_STATUS LpcByteRead(
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IN UINT32 Addr,
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IN OUT UINT8 *Data);
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EFI_STATUS LpcWrite(
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IN UINT32 Addr,
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IN UINT8 *Data,
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IN UINT8 Len);
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#endif
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