/** @file
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Various register numbers and value bits based on the following publications:
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- Intel(R) datasheet 290549-001
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- Intel(R) datasheet 290562-001
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- Intel(R) datasheet 297654-006
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- Intel(R) datasheet 297738-017
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Copyright (C) 2015, Red Hat, Inc.
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Copyright (c) 2014, Gabriel L. Somlo <somlo@cmu.edu>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef __I440FX_PIIX4_H__
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#define __I440FX_PIIX4_H__
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#include <Library/PciLib.h>
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//
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// Host Bridge Device ID (DID) value for I440FX
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//
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#define INTEL_82441_DEVICE_ID 0x1237
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//
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// B/D/F/Type: 0/0/0/PCI
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//
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#define PMC_REGISTER_PIIX4(Offset) PCI_LIB_ADDRESS (0, 0, 0, (Offset))
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#define PIIX4_PAM0 0x59
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#define PIIX4_PAM1 0x5A
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#define PIIX4_PAM2 0x5B
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#define PIIX4_PAM3 0x5C
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#define PIIX4_PAM4 0x5D
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#define PIIX4_PAM5 0x5E
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#define PIIX4_PAM6 0x5F
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//
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// B/D/F/Type: 0/1/3/PCI
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//
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#define POWER_MGMT_REGISTER_PIIX4(Offset) PCI_LIB_ADDRESS (0, 1, 3, (Offset))
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#define PIIX4_PMBA 0x40
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#define PIIX4_PMBA_MASK (BIT15 | BIT14 | BIT13 | BIT12 | BIT11 | \
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BIT10 | BIT9 | BIT8 | BIT7 | BIT6)
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#define PIIX4_PMREGMISC 0x80
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#define PIIX4_PMREGMISC_PMIOSE BIT0
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//
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// IO ports
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//
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#define PIIX4_CPU_HOTPLUG_BASE 0xAF00
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#endif
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