/** @file
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MSR Definitions for Pentium Processors.
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Provides defines for Machine Specific Registers(MSR) indexes. Data structures
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are provided for MSRs that contain one or more bit fields. If the MSR value
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returned is a single 32-bit or 64-bit value, then a data structure is not
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provided for that MSR.
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Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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@par Specification Reference:
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Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
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May 2018, Volume 4: Model-Specific-Registers (MSR)
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**/
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#ifndef __PENTIUM_MSR_H__
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#define __PENTIUM_MSR_H__
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#include <Register/Intel/ArchitecturalMsr.h>
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/**
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Is Pentium Processors?
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@param DisplayFamily Display Family ID
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@param DisplayModel Display Model ID
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@retval TRUE Yes, it is.
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@retval FALSE No, it isn't.
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**/
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#define IS_PENTIUM_PROCESSOR(DisplayFamily, DisplayModel) \
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(DisplayFamily == 0x05 && \
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( \
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DisplayModel == 0x01 || \
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DisplayModel == 0x02 || \
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DisplayModel == 0x04 \
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) \
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)
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/**
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See Section 15.10.2, "Pentium Processor Machine-Check Exception Handling.".
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@param ECX MSR_PENTIUM_P5_MC_ADDR (0x00000000)
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@param EAX Lower 32-bits of MSR value.
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@param EDX Upper 32-bits of MSR value.
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<b>Example usage</b>
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@code
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UINT64 Msr;
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Msr = AsmReadMsr64 (MSR_PENTIUM_P5_MC_ADDR);
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AsmWriteMsr64 (MSR_PENTIUM_P5_MC_ADDR, Msr);
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@endcode
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@note MSR_PENTIUM_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.
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**/
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#define MSR_PENTIUM_P5_MC_ADDR 0x00000000
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/**
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See Section 15.10.2, "Pentium Processor Machine-Check Exception Handling.".
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@param ECX MSR_PENTIUM_P5_MC_TYPE (0x00000001)
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@param EAX Lower 32-bits of MSR value.
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@param EDX Upper 32-bits of MSR value.
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<b>Example usage</b>
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@code
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UINT64 Msr;
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Msr = AsmReadMsr64 (MSR_PENTIUM_P5_MC_TYPE);
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AsmWriteMsr64 (MSR_PENTIUM_P5_MC_TYPE, Msr);
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@endcode
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@note MSR_PENTIUM_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.
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**/
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#define MSR_PENTIUM_P5_MC_TYPE 0x00000001
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/**
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See Section 17.17, "Time-Stamp Counter.".
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@param ECX MSR_PENTIUM_TSC (0x00000010)
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@param EAX Lower 32-bits of MSR value.
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@param EDX Upper 32-bits of MSR value.
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<b>Example usage</b>
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@code
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UINT64 Msr;
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Msr = AsmReadMsr64 (MSR_PENTIUM_TSC);
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AsmWriteMsr64 (MSR_PENTIUM_TSC, Msr);
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@endcode
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@note MSR_PENTIUM_TSC is defined as TSC in SDM.
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**/
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#define MSR_PENTIUM_TSC 0x00000010
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/**
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See Section 18.6.9.1, "Control and Event Select Register (CESR).".
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@param ECX MSR_PENTIUM_CESR (0x00000011)
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@param EAX Lower 32-bits of MSR value.
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@param EDX Upper 32-bits of MSR value.
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<b>Example usage</b>
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@code
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UINT64 Msr;
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Msr = AsmReadMsr64 (MSR_PENTIUM_CESR);
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AsmWriteMsr64 (MSR_PENTIUM_CESR, Msr);
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@endcode
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@note MSR_PENTIUM_CESR is defined as CESR in SDM.
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**/
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#define MSR_PENTIUM_CESR 0x00000011
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/**
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Section 18.6.9.3, "Events Counted.".
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@param ECX MSR_PENTIUM_CTRn
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@param EAX Lower 32-bits of MSR value.
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@param EDX Upper 32-bits of MSR value.
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<b>Example usage</b>
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@code
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UINT64 Msr;
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Msr = AsmReadMsr64 (MSR_PENTIUM_CTR0);
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AsmWriteMsr64 (MSR_PENTIUM_CTR0, Msr);
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@endcode
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@note MSR_PENTIUM_CTR0 is defined as CTR0 in SDM.
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MSR_PENTIUM_CTR1 is defined as CTR1 in SDM.
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@{
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**/
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#define MSR_PENTIUM_CTR0 0x00000012
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#define MSR_PENTIUM_CTR1 0x00000013
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/// @}
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#endif
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