/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Support for Intel Camera Imaging ISP subsystem.
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* Copyright (c) 2015, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef __INPUT_SYSTEM_PRIVATE_H_INCLUDED__
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#define __INPUT_SYSTEM_PRIVATE_H_INCLUDED__
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#include "input_system_public.h"
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#include "device_access.h" /* ia_css_device_load_uint32 */
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#include "assert_support.h" /* assert */
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#include "print_support.h" /* print */
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/* Load the register value */
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static inline hrt_data ibuf_ctrl_reg_load(const ibuf_ctrl_ID_t ID,
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const hrt_address reg)
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{
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assert(ID < N_IBUF_CTRL_ID);
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assert(IBUF_CTRL_BASE[ID] != (hrt_address)-1);
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return ia_css_device_load_uint32(IBUF_CTRL_BASE[ID] + reg * sizeof(hrt_data));
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}
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/* Store a value to the register */
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static inline void ibuf_ctrl_reg_store(const ibuf_ctrl_ID_t ID,
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const hrt_address reg,
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const hrt_data value)
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{
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assert(ID < N_IBUF_CTRL_ID);
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assert(IBUF_CTRL_BASE[ID] != (hrt_address)-1);
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ia_css_device_store_uint32(IBUF_CTRL_BASE[ID] + reg * sizeof(hrt_data), value);
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}
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/* Get the state of the ibuf-controller process */
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static inline void ibuf_ctrl_get_proc_state(const ibuf_ctrl_ID_t ID,
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const u32 proc_id,
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ibuf_ctrl_proc_state_t *state)
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{
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hrt_address reg_bank_offset;
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reg_bank_offset =
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_IBUF_CNTRL_PROC_REG_ALIGN * (1 + proc_id);
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state->num_items =
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ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_NUM_ITEMS_PER_STORE);
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state->num_stores =
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ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_NUM_STORES_PER_FRAME);
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state->dma_channel =
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ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_DMA_CHANNEL);
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state->dma_command =
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ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_DMA_CMD);
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state->ibuf_st_addr =
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ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_BUFFER_START_ADDRESS);
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state->ibuf_stride =
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ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_BUFFER_STRIDE);
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state->ibuf_end_addr =
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ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_BUFFER_END_ADDRESS);
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state->dest_st_addr =
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ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_DEST_START_ADDRESS);
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state->dest_stride =
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ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_DEST_STRIDE);
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state->dest_end_addr =
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ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_DEST_END_ADDRESS);
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state->sync_frame =
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ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_SYNC_FRAME);
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state->sync_command =
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ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_STR2MMIO_SYNC_CMD);
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state->store_command =
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ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_STR2MMIO_STORE_CMD);
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state->shift_returned_items =
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ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_SHIFT_ITEMS);
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state->elems_ibuf =
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ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_ELEMS_P_WORD_IBUF);
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state->elems_dest =
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ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_ELEMS_P_WORD_DEST);
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state->cur_stores =
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ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_CUR_STORES);
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state->cur_acks =
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ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_CUR_ACKS);
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state->cur_s2m_ibuf_addr =
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ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_CUR_S2M_IBUF_ADDR);
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state->cur_dma_ibuf_addr =
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ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_CUR_DMA_IBUF_ADDR);
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state->cur_dma_dest_addr =
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ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_CUR_DMA_DEST_ADDR);
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state->cur_isp_dest_addr =
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ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_CUR_ISP_DEST_ADDR);
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state->dma_cmds_send =
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ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_CUR_NR_DMA_CMDS_SEND);
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state->main_cntrl_state =
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ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_MAIN_CNTRL_STATE);
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state->dma_sync_state =
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ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_DMA_SYNC_STATE);
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state->isp_sync_state =
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ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_ISP_SYNC_STATE);
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}
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/* Get the ibuf-controller state. */
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static inline void ibuf_ctrl_get_state(const ibuf_ctrl_ID_t ID,
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ibuf_ctrl_state_t *state)
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{
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u32 i;
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state->recalc_words =
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ibuf_ctrl_reg_load(ID, _IBUF_CNTRL_RECALC_WORDS_STATUS);
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state->arbiters =
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ibuf_ctrl_reg_load(ID, _IBUF_CNTRL_ARBITERS_STATUS);
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/*
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* Get the values of the register-set per
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* ibuf-controller process.
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*/
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for (i = 0; i < N_IBUF_CTRL_PROCS[ID]; i++) {
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ibuf_ctrl_get_proc_state(
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ID,
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i,
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&state->proc_state[i]);
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}
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}
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/* Dump the ibuf-controller state */
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static inline void ibuf_ctrl_dump_state(const ibuf_ctrl_ID_t ID,
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ibuf_ctrl_state_t *state)
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{
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u32 i;
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ia_css_print("IBUF controller ID %d recalculate words 0x%x\n", ID,
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state->recalc_words);
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ia_css_print("IBUF controller ID %d arbiters 0x%x\n", ID, state->arbiters);
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/*
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* Dump the values of the register-set per
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* ibuf-controller process.
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*/
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for (i = 0; i < N_IBUF_CTRL_PROCS[ID]; i++) {
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ia_css_print("IBUF controller ID %d Process ID %d num_items 0x%x\n", ID, i,
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state->proc_state[i].num_items);
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ia_css_print("IBUF controller ID %d Process ID %d num_stores 0x%x\n", ID, i,
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state->proc_state[i].num_stores);
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ia_css_print("IBUF controller ID %d Process ID %d dma_channel 0x%x\n", ID, i,
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state->proc_state[i].dma_channel);
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ia_css_print("IBUF controller ID %d Process ID %d dma_command 0x%x\n", ID, i,
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state->proc_state[i].dma_command);
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ia_css_print("IBUF controller ID %d Process ID %d ibuf_st_addr 0x%x\n", ID, i,
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state->proc_state[i].ibuf_st_addr);
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ia_css_print("IBUF controller ID %d Process ID %d ibuf_stride 0x%x\n", ID, i,
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state->proc_state[i].ibuf_stride);
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ia_css_print("IBUF controller ID %d Process ID %d ibuf_end_addr 0x%x\n", ID, i,
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state->proc_state[i].ibuf_end_addr);
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ia_css_print("IBUF controller ID %d Process ID %d dest_st_addr 0x%x\n", ID, i,
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state->proc_state[i].dest_st_addr);
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ia_css_print("IBUF controller ID %d Process ID %d dest_stride 0x%x\n", ID, i,
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state->proc_state[i].dest_stride);
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ia_css_print("IBUF controller ID %d Process ID %d dest_end_addr 0x%x\n", ID, i,
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state->proc_state[i].dest_end_addr);
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ia_css_print("IBUF controller ID %d Process ID %d sync_frame 0x%x\n", ID, i,
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state->proc_state[i].sync_frame);
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ia_css_print("IBUF controller ID %d Process ID %d sync_command 0x%x\n", ID, i,
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state->proc_state[i].sync_command);
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ia_css_print("IBUF controller ID %d Process ID %d store_command 0x%x\n", ID, i,
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state->proc_state[i].store_command);
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ia_css_print("IBUF controller ID %d Process ID %d shift_returned_items 0x%x\n",
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ID, i,
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state->proc_state[i].shift_returned_items);
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ia_css_print("IBUF controller ID %d Process ID %d elems_ibuf 0x%x\n", ID, i,
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state->proc_state[i].elems_ibuf);
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ia_css_print("IBUF controller ID %d Process ID %d elems_dest 0x%x\n", ID, i,
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state->proc_state[i].elems_dest);
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ia_css_print("IBUF controller ID %d Process ID %d cur_stores 0x%x\n", ID, i,
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state->proc_state[i].cur_stores);
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ia_css_print("IBUF controller ID %d Process ID %d cur_acks 0x%x\n", ID, i,
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state->proc_state[i].cur_acks);
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ia_css_print("IBUF controller ID %d Process ID %d cur_s2m_ibuf_addr 0x%x\n", ID,
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i,
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state->proc_state[i].cur_s2m_ibuf_addr);
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ia_css_print("IBUF controller ID %d Process ID %d cur_dma_ibuf_addr 0x%x\n", ID,
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i,
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state->proc_state[i].cur_dma_ibuf_addr);
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ia_css_print("IBUF controller ID %d Process ID %d cur_dma_dest_addr 0x%x\n", ID,
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i,
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state->proc_state[i].cur_dma_dest_addr);
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ia_css_print("IBUF controller ID %d Process ID %d cur_isp_dest_addr 0x%x\n", ID,
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i,
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state->proc_state[i].cur_isp_dest_addr);
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ia_css_print("IBUF controller ID %d Process ID %d dma_cmds_send 0x%x\n", ID, i,
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state->proc_state[i].dma_cmds_send);
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ia_css_print("IBUF controller ID %d Process ID %d main_cntrl_state 0x%x\n", ID,
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i,
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state->proc_state[i].main_cntrl_state);
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ia_css_print("IBUF controller ID %d Process ID %d dma_sync_state 0x%x\n", ID, i,
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state->proc_state[i].dma_sync_state);
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ia_css_print("IBUF controller ID %d Process ID %d isp_sync_state 0x%x\n", ID, i,
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state->proc_state[i].isp_sync_state);
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}
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}
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static inline input_system_err_t
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input_system_get_state(const input_system_ID_t ID,
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input_system_state_t *state)
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{
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u32 i;
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(void)(ID);
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/* get the states of all CSI RX frontend devices */
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for (i = 0; i < N_CSI_RX_FRONTEND_ID; i++) {
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csi_rx_fe_ctrl_get_state(
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(csi_rx_frontend_ID_t)i,
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&state->csi_rx_fe_ctrl_state[i]);
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}
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/* get the states of all CIS RX backend devices */
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for (i = 0; i < N_CSI_RX_BACKEND_ID; i++) {
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csi_rx_be_ctrl_get_state(
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(csi_rx_backend_ID_t)i,
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&state->csi_rx_be_ctrl_state[i]);
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}
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/* get the states of all pixelgen devices */
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for (i = 0; i < N_PIXELGEN_ID; i++) {
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pixelgen_ctrl_get_state(
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(pixelgen_ID_t)i,
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&state->pixelgen_ctrl_state[i]);
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}
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/* get the states of all stream2mmio devices */
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for (i = 0; i < N_STREAM2MMIO_ID; i++) {
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stream2mmio_get_state(
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(stream2mmio_ID_t)i,
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&state->stream2mmio_state[i]);
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}
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/* get the states of all ibuf-controller devices */
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for (i = 0; i < N_IBUF_CTRL_ID; i++) {
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ibuf_ctrl_get_state(
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(ibuf_ctrl_ID_t)i,
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&state->ibuf_ctrl_state[i]);
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}
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/* get the states of all isys irq controllers */
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for (i = 0; i < N_ISYS_IRQ_ID; i++) {
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isys_irqc_state_get((isys_irq_ID_t)i, &state->isys_irqc_state[i]);
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}
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/* TODO: get the states of all ISYS2401 DMA devices */
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for (i = 0; i < N_ISYS2401_DMA_ID; i++) {
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}
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return INPUT_SYSTEM_ERR_NO_ERROR;
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}
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static inline void input_system_dump_state(const input_system_ID_t ID,
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input_system_state_t *state)
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{
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u32 i;
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(void)(ID);
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/* dump the states of all CSI RX frontend devices */
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for (i = 0; i < N_CSI_RX_FRONTEND_ID; i++) {
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csi_rx_fe_ctrl_dump_state(
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(csi_rx_frontend_ID_t)i,
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&state->csi_rx_fe_ctrl_state[i]);
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}
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/* dump the states of all CIS RX backend devices */
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for (i = 0; i < N_CSI_RX_BACKEND_ID; i++) {
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csi_rx_be_ctrl_dump_state(
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(csi_rx_backend_ID_t)i,
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&state->csi_rx_be_ctrl_state[i]);
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}
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/* dump the states of all pixelgen devices */
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for (i = 0; i < N_PIXELGEN_ID; i++) {
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pixelgen_ctrl_dump_state(
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(pixelgen_ID_t)i,
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&state->pixelgen_ctrl_state[i]);
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}
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/* dump the states of all st2mmio devices */
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for (i = 0; i < N_STREAM2MMIO_ID; i++) {
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stream2mmio_dump_state(
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(stream2mmio_ID_t)i,
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&state->stream2mmio_state[i]);
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}
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/* dump the states of all ibuf-controller devices */
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for (i = 0; i < N_IBUF_CTRL_ID; i++) {
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ibuf_ctrl_dump_state(
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(ibuf_ctrl_ID_t)i,
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&state->ibuf_ctrl_state[i]);
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}
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/* dump the states of all isys irq controllers */
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for (i = 0; i < N_ISYS_IRQ_ID; i++) {
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isys_irqc_state_dump((isys_irq_ID_t)i, &state->isys_irqc_state[i]);
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}
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/* TODO: dump the states of all ISYS2401 DMA devices */
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for (i = 0; i < N_ISYS2401_DMA_ID; i++) {
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}
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return;
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}
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#endif /* __INPUT_SYSTEM_PRIVATE_H_INCLUDED__ */
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