/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Support for Intel Camera Imaging ISP subsystem.
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* Copyright (c) 2015, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef __INPUT_SYSTEM_PUBLIC_H_INCLUDED__
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#define __INPUT_SYSTEM_PUBLIC_H_INCLUDED__
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#include <type_support.h>
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#ifdef ISP2401
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#include "isys_public.h"
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#else
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typedef struct input_system_state_s input_system_state_t;
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typedef struct receiver_state_s receiver_state_t;
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/*! Read the state of INPUT_SYSTEM[ID]
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\param ID[in] INPUT_SYSTEM identifier
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\param state[out] input system state structure
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\return none, state = INPUT_SYSTEM[ID].state
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*/
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void input_system_get_state(
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const input_system_ID_t ID,
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input_system_state_t *state);
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/*! Read the state of RECEIVER[ID]
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\param ID[in] RECEIVER identifier
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\param state[out] receiver state structure
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\return none, state = RECEIVER[ID].state
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*/
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void receiver_get_state(
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const rx_ID_t ID,
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receiver_state_t *state);
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/*! Flag whether a MIPI format is YUV420
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\param mipi_format[in] MIPI format
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\return mipi_format == YUV420
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*/
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bool is_mipi_format_yuv420(
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const mipi_format_t mipi_format);
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/*! Set compression parameters for cfg[cfg_ID] of RECEIVER[ID]
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\param ID[in] RECEIVER identifier
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\param cfg_ID[in] Configuration identifier
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\param comp[in] Compression method
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\param pred[in] Predictor method
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\NOTE: the storage of compression configuration is
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implementation specific. The config can be
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carried either on MIPI ports or on MIPI channels
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\return none, RECEIVER[ID].cfg[cfg_ID] = {comp, pred}
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*/
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void receiver_set_compression(
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const rx_ID_t ID,
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const unsigned int cfg_ID,
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const mipi_compressor_t comp,
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const mipi_predictor_t pred);
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/*! Enable PORT[port_ID] of RECEIVER[ID]
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\param ID[in] RECEIVER identifier
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\param port_ID[in] mipi PORT identifier
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\param cnd[in] irq predicate
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\return None, enable(RECEIVER[ID].PORT[port_ID])
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*/
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void receiver_port_enable(
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const rx_ID_t ID,
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const enum mipi_port_id port_ID,
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const bool cnd);
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/*! Flag if PORT[port_ID] of RECEIVER[ID] is enabled
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\param ID[in] RECEIVER identifier
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\param port_ID[in] mipi PORT identifier
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\return enable(RECEIVER[ID].PORT[port_ID]) == true
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*/
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bool is_receiver_port_enabled(
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const rx_ID_t ID,
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const enum mipi_port_id port_ID);
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/*! Enable the IRQ channels of PORT[port_ID] of RECEIVER[ID]
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\param ID[in] RECEIVER identifier
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\param port_ID[in] mipi PORT identifier
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\param irq_info[in] irq channels
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\return None, enable(RECEIVER[ID].PORT[port_ID].irq_info)
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*/
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void receiver_irq_enable(
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const rx_ID_t ID,
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const enum mipi_port_id port_ID,
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const rx_irq_info_t irq_info);
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/*! Return the IRQ status of PORT[port_ID] of RECEIVER[ID]
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\param ID[in] RECEIVER identifier
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\param port_ID[in] mipi PORT identifier
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\return RECEIVER[ID].PORT[port_ID].irq_info
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*/
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rx_irq_info_t receiver_get_irq_info(
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const rx_ID_t ID,
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const enum mipi_port_id port_ID);
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/*! Clear the IRQ status of PORT[port_ID] of RECEIVER[ID]
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\param ID[in] RECEIVER identifier
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\param port_ID[in] mipi PORT identifier
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\param irq_info[in] irq status
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\return None, clear(RECEIVER[ID].PORT[port_ID].irq_info)
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*/
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void receiver_irq_clear(
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const rx_ID_t ID,
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const enum mipi_port_id port_ID,
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const rx_irq_info_t irq_info);
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/*! Write to a control register of INPUT_SYSTEM[ID]
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\param ID[in] INPUT_SYSTEM identifier
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\param reg[in] register index
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\param value[in] The data to be written
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\return none, INPUT_SYSTEM[ID].ctrl[reg] = value
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*/
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STORAGE_CLASS_INPUT_SYSTEM_H void input_system_reg_store(
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const input_system_ID_t ID,
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const hrt_address reg,
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const hrt_data value);
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/*! Read from a control register of INPUT_SYSTEM[ID]
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\param ID[in] INPUT_SYSTEM identifier
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\param reg[in] register index
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\param value[in] The data to be written
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\return INPUT_SYSTEM[ID].ctrl[reg]
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*/
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STORAGE_CLASS_INPUT_SYSTEM_H hrt_data input_system_reg_load(
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const input_system_ID_t ID,
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const hrt_address reg);
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/*! Write to a control register of RECEIVER[ID]
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\param ID[in] RECEIVER identifier
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\param reg[in] register index
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\param value[in] The data to be written
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\return none, RECEIVER[ID].ctrl[reg] = value
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*/
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STORAGE_CLASS_INPUT_SYSTEM_H void receiver_reg_store(
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const rx_ID_t ID,
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const hrt_address reg,
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const hrt_data value);
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/*! Read from a control register of RECEIVER[ID]
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\param ID[in] RECEIVER identifier
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\param reg[in] register index
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\param value[in] The data to be written
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\return RECEIVER[ID].ctrl[reg]
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*/
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STORAGE_CLASS_INPUT_SYSTEM_H hrt_data receiver_reg_load(
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const rx_ID_t ID,
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const hrt_address reg);
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/*! Write to a control register of PORT[port_ID] of RECEIVER[ID]
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\param ID[in] RECEIVER identifier
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\param port_ID[in] mipi PORT identifier
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\param reg[in] register index
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\param value[in] The data to be written
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\return none, RECEIVER[ID].PORT[port_ID].ctrl[reg] = value
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*/
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STORAGE_CLASS_INPUT_SYSTEM_H void receiver_port_reg_store(
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const rx_ID_t ID,
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const enum mipi_port_id port_ID,
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const hrt_address reg,
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const hrt_data value);
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/*! Read from a control register PORT[port_ID] of of RECEIVER[ID]
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\param ID[in] RECEIVER identifier
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\param port_ID[in] mipi PORT identifier
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\param reg[in] register index
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\param value[in] The data to be written
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\return RECEIVER[ID].PORT[port_ID].ctrl[reg]
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*/
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STORAGE_CLASS_INPUT_SYSTEM_H hrt_data receiver_port_reg_load(
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const rx_ID_t ID,
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const enum mipi_port_id port_ID,
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const hrt_address reg);
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/*! Write to a control register of SUB_SYSTEM[sub_ID] of INPUT_SYSTEM[ID]
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\param ID[in] INPUT_SYSTEM identifier
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\param port_ID[in] sub system identifier
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\param reg[in] register index
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\param value[in] The data to be written
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\return none, INPUT_SYSTEM[ID].SUB_SYSTEM[sub_ID].ctrl[reg] = value
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*/
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STORAGE_CLASS_INPUT_SYSTEM_H void input_system_sub_system_reg_store(
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const input_system_ID_t ID,
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const sub_system_ID_t sub_ID,
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const hrt_address reg,
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const hrt_data value);
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/*! Read from a control register SUB_SYSTEM[sub_ID] of INPUT_SYSTEM[ID]
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\param ID[in] INPUT_SYSTEM identifier
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\param port_ID[in] sub system identifier
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\param reg[in] register index
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\param value[in] The data to be written
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\return INPUT_SYSTEM[ID].SUB_SYSTEM[sub_ID].ctrl[reg]
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*/
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STORAGE_CLASS_INPUT_SYSTEM_H hrt_data input_system_sub_system_reg_load(
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const input_system_ID_t ID,
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const sub_system_ID_t sub_ID,
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const hrt_address reg);
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///////////////////////////////////////////////////////////////////////////
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//
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// Functions for configuration phase on input system.
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//
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///////////////////////////////////////////////////////////////////////////
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// Function that resets current configuration.
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// remove the argument since it should be private.
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input_system_err_t input_system_configuration_reset(void);
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// Function that commits current configuration.
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// remove the argument since it should be private.
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input_system_err_t input_system_configuration_commit(void);
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///////////////////////////////////////////////////////////////////////////
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//
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// User functions:
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// (encoded generic function)
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// - no checking
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// - decoding name and agruments into the generic (channel) configuration
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// function.
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//
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///////////////////////////////////////////////////////////////////////////
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// FIFO channel config function user
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input_system_err_t input_system_csi_fifo_channel_cfg(
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u32 ch_id,
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input_system_csi_port_t port,
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backend_channel_cfg_t backend_ch,
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target_cfg2400_t target
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);
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input_system_err_t input_system_csi_fifo_channel_with_counting_cfg(
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u32 ch_id,
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u32 nof_frame,
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input_system_csi_port_t port,
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backend_channel_cfg_t backend_ch,
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u32 mem_region_size,
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u32 nof_mem_regions,
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target_cfg2400_t target
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);
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// SRAM channel config function user
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input_system_err_t input_system_csi_sram_channel_cfg(
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u32 ch_id,
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input_system_csi_port_t port,
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backend_channel_cfg_t backend_ch,
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u32 csi_mem_region_size,
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u32 csi_nof_mem_regions,
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target_cfg2400_t target
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);
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//XMEM channel config function user
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input_system_err_t input_system_csi_xmem_channel_cfg(
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u32 ch_id,
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input_system_csi_port_t port,
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backend_channel_cfg_t backend_ch,
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u32 mem_region_size,
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u32 nof_mem_regions,
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u32 acq_mem_region_size,
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u32 acq_nof_mem_regions,
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target_cfg2400_t target,
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uint32_t nof_xmem_buffers
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);
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input_system_err_t input_system_csi_xmem_capture_only_channel_cfg(
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u32 ch_id,
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u32 nof_frames,
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input_system_csi_port_t port,
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u32 csi_mem_region_size,
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u32 csi_nof_mem_regions,
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u32 acq_mem_region_size,
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u32 acq_nof_mem_regions,
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target_cfg2400_t target
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);
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input_system_err_t input_system_csi_xmem_acquire_only_channel_cfg(
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u32 ch_id,
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u32 nof_frames,
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input_system_csi_port_t port,
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backend_channel_cfg_t backend_ch,
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u32 acq_mem_region_size,
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u32 acq_nof_mem_regions,
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target_cfg2400_t target
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);
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// Non - CSI channel config function user
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input_system_err_t input_system_prbs_channel_cfg(
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u32 ch_id,
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u32 nof_frames,
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u32 seed,
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u32 sync_gen_width,
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u32 sync_gen_height,
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u32 sync_gen_hblank_cycles,
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u32 sync_gen_vblank_cycles,
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target_cfg2400_t target
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);
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input_system_err_t input_system_tpg_channel_cfg(
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u32 ch_id,
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u32 nof_frames,//not used yet
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u32 x_mask,
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u32 y_mask,
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u32 x_delta,
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u32 y_delta,
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u32 xy_mask,
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u32 sync_gen_width,
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u32 sync_gen_height,
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u32 sync_gen_hblank_cycles,
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u32 sync_gen_vblank_cycles,
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target_cfg2400_t target
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);
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input_system_err_t input_system_gpfifo_channel_cfg(
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u32 ch_id,
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u32 nof_frames,
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target_cfg2400_t target
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);
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#endif /* #ifdef ISP2401 */
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#endif /* __INPUT_SYSTEM_PUBLIC_H_INCLUDED__ */
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