// SPDX-License-Identifier: GPL-2.0
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/*
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* Support for Intel Camera Imaging ISP subsystem.
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* Copyright (c) 2010-2015, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include "assert_support.h"
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#include "irq.h"
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#ifndef __INLINE_GP_DEVICE__
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#define __INLINE_GP_DEVICE__
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#endif
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#include "gp_device.h" /* _REG_GP_IRQ_REQUEST_ADDR */
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static inline void irq_wait_for_write_complete(
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const irq_ID_t ID);
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static inline bool any_irq_channel_enabled(
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const irq_ID_t ID);
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static inline irq_ID_t virq_get_irq_id(const enum virq_id irq_ID,
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unsigned int *channel_ID);
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#ifndef __INLINE_IRQ__
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#include "irq_private.h"
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#endif /* __INLINE_IRQ__ */
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static unsigned short IRQ_N_CHANNEL[N_IRQ_ID] = {
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IRQ0_ID_N_CHANNEL,
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IRQ1_ID_N_CHANNEL,
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IRQ2_ID_N_CHANNEL,
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IRQ3_ID_N_CHANNEL
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};
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static unsigned short IRQ_N_ID_OFFSET[N_IRQ_ID + 1] = {
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IRQ0_ID_OFFSET,
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IRQ1_ID_OFFSET,
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IRQ2_ID_OFFSET,
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IRQ3_ID_OFFSET,
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IRQ_END_OFFSET
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};
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static enum virq_id IRQ_NESTING_ID[N_IRQ_ID] = {
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N_virq_id,
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virq_ifmt,
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virq_isys,
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virq_isel
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};
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void irq_clear_all(
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const irq_ID_t ID)
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{
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hrt_data mask = 0xFFFFFFFF;
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assert(ID < N_IRQ_ID);
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assert(IRQ_N_CHANNEL[ID] <= HRT_DATA_WIDTH);
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if (IRQ_N_CHANNEL[ID] < HRT_DATA_WIDTH) {
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mask = ~((~(hrt_data)0) >> IRQ_N_CHANNEL[ID]);
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}
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irq_reg_store(ID,
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_HRT_IRQ_CONTROLLER_CLEAR_REG_IDX, mask);
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return;
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}
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/*
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* Do we want the user to be able to set the signalling method ?
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*/
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void irq_enable_channel(
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const irq_ID_t ID,
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const unsigned int irq_id)
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{
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unsigned int mask = irq_reg_load(ID,
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_HRT_IRQ_CONTROLLER_MASK_REG_IDX);
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unsigned int enable = irq_reg_load(ID,
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_HRT_IRQ_CONTROLLER_ENABLE_REG_IDX);
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unsigned int edge_in = irq_reg_load(ID,
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_HRT_IRQ_CONTROLLER_EDGE_REG_IDX);
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unsigned int me = 1U << irq_id;
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assert(ID < N_IRQ_ID);
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assert(irq_id < IRQ_N_CHANNEL[ID]);
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mask |= me;
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enable |= me;
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edge_in |= me; /* rising edge */
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/* to avoid mishaps configuration must follow the following order */
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/* mask this interrupt */
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irq_reg_store(ID,
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_HRT_IRQ_CONTROLLER_MASK_REG_IDX, mask & ~me);
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/* rising edge at input */
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irq_reg_store(ID,
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_HRT_IRQ_CONTROLLER_EDGE_REG_IDX, edge_in);
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/* enable interrupt to output */
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irq_reg_store(ID,
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_HRT_IRQ_CONTROLLER_ENABLE_REG_IDX, enable);
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/* clear current irq only */
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irq_reg_store(ID,
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_HRT_IRQ_CONTROLLER_CLEAR_REG_IDX, me);
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/* unmask interrupt from input */
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irq_reg_store(ID,
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_HRT_IRQ_CONTROLLER_MASK_REG_IDX, mask);
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irq_wait_for_write_complete(ID);
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return;
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}
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void irq_enable_pulse(
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const irq_ID_t ID,
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bool pulse)
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{
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unsigned int edge_out = 0x0;
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if (pulse) {
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edge_out = 0xffffffff;
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}
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/* output is given as edge, not pulse */
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irq_reg_store(ID,
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_HRT_IRQ_CONTROLLER_EDGE_NOT_PULSE_REG_IDX, edge_out);
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return;
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}
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void irq_disable_channel(
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const irq_ID_t ID,
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const unsigned int irq_id)
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{
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unsigned int mask = irq_reg_load(ID,
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_HRT_IRQ_CONTROLLER_MASK_REG_IDX);
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unsigned int enable = irq_reg_load(ID,
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_HRT_IRQ_CONTROLLER_ENABLE_REG_IDX);
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unsigned int me = 1U << irq_id;
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assert(ID < N_IRQ_ID);
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assert(irq_id < IRQ_N_CHANNEL[ID]);
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mask &= ~me;
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enable &= ~me;
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/* enable interrupt to output */
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irq_reg_store(ID,
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_HRT_IRQ_CONTROLLER_ENABLE_REG_IDX, enable);
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/* unmask interrupt from input */
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irq_reg_store(ID,
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_HRT_IRQ_CONTROLLER_MASK_REG_IDX, mask);
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/* clear current irq only */
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irq_reg_store(ID,
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_HRT_IRQ_CONTROLLER_CLEAR_REG_IDX, me);
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irq_wait_for_write_complete(ID);
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return;
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}
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enum hrt_isp_css_irq_status irq_get_channel_id(
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const irq_ID_t ID,
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unsigned int *irq_id)
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{
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unsigned int irq_status = irq_reg_load(ID,
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_HRT_IRQ_CONTROLLER_STATUS_REG_IDX);
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unsigned int idx;
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enum hrt_isp_css_irq_status status = hrt_isp_css_irq_status_success;
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assert(ID < N_IRQ_ID);
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assert(irq_id);
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/* find the first irq bit */
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for (idx = 0; idx < IRQ_N_CHANNEL[ID]; idx++) {
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if (irq_status & (1U << idx))
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break;
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}
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if (idx == IRQ_N_CHANNEL[ID])
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return hrt_isp_css_irq_status_error;
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/* now check whether there are more bits set */
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if (irq_status != (1U << idx))
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status = hrt_isp_css_irq_status_more_irqs;
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irq_reg_store(ID,
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_HRT_IRQ_CONTROLLER_CLEAR_REG_IDX, 1U << idx);
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irq_wait_for_write_complete(ID);
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if (irq_id)
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*irq_id = (unsigned int)idx;
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return status;
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}
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static const hrt_address IRQ_REQUEST_ADDR[N_IRQ_SW_CHANNEL_ID] = {
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_REG_GP_IRQ_REQUEST0_ADDR,
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_REG_GP_IRQ_REQUEST1_ADDR
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};
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void irq_raise(
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const irq_ID_t ID,
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const irq_sw_channel_id_t irq_id)
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{
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hrt_address addr;
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OP___assert(ID == IRQ0_ID);
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OP___assert(IRQ_BASE[ID] != (hrt_address)-1);
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OP___assert(irq_id < N_IRQ_SW_CHANNEL_ID);
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(void)ID;
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addr = IRQ_REQUEST_ADDR[irq_id];
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/* The SW IRQ pins are remapped to offset zero */
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gp_device_reg_store(GP_DEVICE0_ID,
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(unsigned int)addr, 1);
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gp_device_reg_store(GP_DEVICE0_ID,
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(unsigned int)addr, 0);
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return;
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}
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void irq_controller_get_state(const irq_ID_t ID,
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struct irq_controller_state *state)
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{
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assert(ID < N_IRQ_ID);
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assert(state);
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state->irq_edge = irq_reg_load(ID,
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_HRT_IRQ_CONTROLLER_EDGE_REG_IDX);
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state->irq_mask = irq_reg_load(ID,
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_HRT_IRQ_CONTROLLER_MASK_REG_IDX);
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state->irq_status = irq_reg_load(ID,
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_HRT_IRQ_CONTROLLER_STATUS_REG_IDX);
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state->irq_enable = irq_reg_load(ID,
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_HRT_IRQ_CONTROLLER_ENABLE_REG_IDX);
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state->irq_level_not_pulse = irq_reg_load(ID,
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_HRT_IRQ_CONTROLLER_EDGE_NOT_PULSE_REG_IDX);
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return;
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}
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bool any_virq_signal(void)
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{
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unsigned int irq_status = irq_reg_load(IRQ0_ID,
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_HRT_IRQ_CONTROLLER_STATUS_REG_IDX);
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return (irq_status != 0);
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}
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void cnd_virq_enable_channel(
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const enum virq_id irq_ID,
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const bool en)
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{
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irq_ID_t i;
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unsigned int channel_ID;
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irq_ID_t ID = virq_get_irq_id(irq_ID, &channel_ID);
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assert(ID < N_IRQ_ID);
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for (i = IRQ1_ID; i < N_IRQ_ID; i++) {
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/* It is not allowed to enable the pin of a nested IRQ directly */
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assert(irq_ID != IRQ_NESTING_ID[i]);
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}
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if (en) {
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irq_enable_channel(ID, channel_ID);
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if (IRQ_NESTING_ID[ID] != N_virq_id) {
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/* Single level nesting, otherwise we'd need to recurse */
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irq_enable_channel(IRQ0_ID, IRQ_NESTING_ID[ID]);
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}
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} else {
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irq_disable_channel(ID, channel_ID);
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if ((IRQ_NESTING_ID[ID] != N_virq_id) && !any_irq_channel_enabled(ID)) {
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/* Only disable the top if the nested ones are empty */
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irq_disable_channel(IRQ0_ID, IRQ_NESTING_ID[ID]);
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}
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}
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return;
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}
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void virq_clear_all(void)
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{
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irq_ID_t irq_id;
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for (irq_id = (irq_ID_t)0; irq_id < N_IRQ_ID; irq_id++) {
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irq_clear_all(irq_id);
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}
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return;
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}
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enum hrt_isp_css_irq_status
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virq_get_channel_signals(struct virq_info *irq_info)
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{
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enum hrt_isp_css_irq_status irq_status = hrt_isp_css_irq_status_error;
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irq_ID_t ID;
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assert(irq_info);
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for (ID = (irq_ID_t)0 ; ID < N_IRQ_ID; ID++) {
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if (any_irq_channel_enabled(ID)) {
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hrt_data irq_data = irq_reg_load(ID,
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_HRT_IRQ_CONTROLLER_STATUS_REG_IDX);
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if (irq_data != 0) {
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/* The error condition is an IRQ pulse received with no IRQ status written */
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irq_status = hrt_isp_css_irq_status_success;
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}
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irq_info->irq_status_reg[ID] |= irq_data;
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irq_reg_store(ID,
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_HRT_IRQ_CONTROLLER_CLEAR_REG_IDX, irq_data);
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irq_wait_for_write_complete(ID);
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}
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}
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return irq_status;
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}
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void virq_clear_info(struct virq_info *irq_info)
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{
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irq_ID_t ID;
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assert(irq_info);
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for (ID = (irq_ID_t)0 ; ID < N_IRQ_ID; ID++) {
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irq_info->irq_status_reg[ID] = 0;
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}
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return;
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}
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enum hrt_isp_css_irq_status virq_get_channel_id(
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enum virq_id *irq_id)
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{
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unsigned int irq_status = irq_reg_load(IRQ0_ID,
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_HRT_IRQ_CONTROLLER_STATUS_REG_IDX);
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unsigned int idx;
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enum hrt_isp_css_irq_status status = hrt_isp_css_irq_status_success;
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irq_ID_t ID;
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assert(irq_id);
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/* find the first irq bit on device 0 */
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for (idx = 0; idx < IRQ_N_CHANNEL[IRQ0_ID]; idx++) {
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if (irq_status & (1U << idx))
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break;
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}
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if (idx == IRQ_N_CHANNEL[IRQ0_ID]) {
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return hrt_isp_css_irq_status_error;
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}
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/* Check whether there are more bits set on device 0 */
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if (irq_status != (1U << idx)) {
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status = hrt_isp_css_irq_status_more_irqs;
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}
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/* Check whether we have an IRQ on one of the nested devices */
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for (ID = N_IRQ_ID - 1 ; ID > (irq_ID_t)0; ID--) {
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if (IRQ_NESTING_ID[ID] == (enum virq_id)idx) {
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break;
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}
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}
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/* If we have a nested IRQ, load that state, discard the device 0 state */
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if (ID != IRQ0_ID) {
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irq_status = irq_reg_load(ID,
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_HRT_IRQ_CONTROLLER_STATUS_REG_IDX);
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/* find the first irq bit on device "id" */
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for (idx = 0; idx < IRQ_N_CHANNEL[ID]; idx++) {
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if (irq_status & (1U << idx))
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break;
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}
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if (idx == IRQ_N_CHANNEL[ID]) {
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return hrt_isp_css_irq_status_error;
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}
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/* Alternatively check whether there are more bits set on this device */
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if (irq_status != (1U << idx)) {
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status = hrt_isp_css_irq_status_more_irqs;
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} else {
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/* If this device is empty, clear the state on device 0 */
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irq_reg_store(IRQ0_ID,
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_HRT_IRQ_CONTROLLER_CLEAR_REG_IDX, 1U << IRQ_NESTING_ID[ID]);
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}
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} /* if (ID != IRQ0_ID) */
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/* Here we proceed to clear the IRQ on detected device, if no nested IRQ, this is device 0 */
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irq_reg_store(ID,
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_HRT_IRQ_CONTROLLER_CLEAR_REG_IDX, 1U << idx);
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irq_wait_for_write_complete(ID);
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idx += IRQ_N_ID_OFFSET[ID];
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if (irq_id)
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*irq_id = (enum virq_id)idx;
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return status;
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}
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static inline void irq_wait_for_write_complete(
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const irq_ID_t ID)
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{
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assert(ID < N_IRQ_ID);
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assert(IRQ_BASE[ID] != (hrt_address)-1);
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(void)ia_css_device_load_uint32(IRQ_BASE[ID] +
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_HRT_IRQ_CONTROLLER_ENABLE_REG_IDX * sizeof(hrt_data));
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}
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static inline bool any_irq_channel_enabled(
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const irq_ID_t ID)
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{
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hrt_data en_reg;
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assert(ID < N_IRQ_ID);
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en_reg = irq_reg_load(ID,
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_HRT_IRQ_CONTROLLER_ENABLE_REG_IDX);
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return (en_reg != 0);
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}
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static inline irq_ID_t virq_get_irq_id(
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const enum virq_id irq_ID,
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unsigned int *channel_ID)
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{
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irq_ID_t ID;
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assert(channel_ID);
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for (ID = (irq_ID_t)0 ; ID < N_IRQ_ID; ID++) {
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if (irq_ID < IRQ_N_ID_OFFSET[ID + 1]) {
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break;
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}
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}
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*channel_ID = (unsigned int)irq_ID - IRQ_N_ID_OFFSET[ID];
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return ID;
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}
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