// SPDX-License-Identifier: GPL-2.0
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/*
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* Support for Intel Camera Imaging ISP subsystem.
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* Copyright (c) 2010-2016, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <linux/kernel.h>
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#include "dma.h"
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#include "assert_support.h"
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#ifndef __INLINE_DMA__
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#include "dma_private.h"
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#endif /* __INLINE_DMA__ */
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void dma_get_state(const dma_ID_t ID, dma_state_t *state)
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{
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int i;
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hrt_data tmp;
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assert(ID < N_DMA_ID);
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assert(state);
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tmp = dma_reg_load(ID, DMA_COMMAND_FSM_REG_IDX);
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//reg [3:0] : flags error [3], stall, run, idle [0]
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//reg [9:4] : command
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//reg[14:10] : channel
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//reg [23:15] : param
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state->fsm_command_idle = tmp & 0x1;
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state->fsm_command_run = tmp & 0x2;
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state->fsm_command_stalling = tmp & 0x4;
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state->fsm_command_error = tmp & 0x8;
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state->last_command_channel = (tmp >> 10 & 0x1F);
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state->last_command_param = (tmp >> 15 & 0x0F);
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tmp = (tmp >> 4) & 0x3F;
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/* state->last_command = (dma_commands_t)tmp; */
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/* if the enumerator is made non-linear */
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/* AM: the list below does not cover all the cases*/
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/* and these are not correct */
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/* therefore for just dumpinmg this command*/
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state->last_command = tmp;
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/*
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if (tmp == 0)
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state->last_command = DMA_COMMAND_READ;
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if (tmp == 1)
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state->last_command = DMA_COMMAND_WRITE;
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if (tmp == 2)
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state->last_command = DMA_COMMAND_SET_CHANNEL;
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if (tmp == 3)
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state->last_command = DMA_COMMAND_SET_PARAM;
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if (tmp == 4)
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state->last_command = DMA_COMMAND_READ_SPECIFIC;
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if (tmp == 5)
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state->last_command = DMA_COMMAND_WRITE_SPECIFIC;
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if (tmp == 8)
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state->last_command = DMA_COMMAND_INIT;
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if (tmp == 12)
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state->last_command = DMA_COMMAND_INIT_SPECIFIC;
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if (tmp == 15)
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state->last_command = DMA_COMMAND_RST;
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*/
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/* No sub-fields, idx = 0 */
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state->current_command = dma_reg_load(ID,
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DMA_CG_INFO_REG_IDX(0, _DMA_FSM_GROUP_CMD_IDX));
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state->current_addr_a = dma_reg_load(ID,
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DMA_CG_INFO_REG_IDX(0, _DMA_FSM_GROUP_ADDR_A_IDX));
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state->current_addr_b = dma_reg_load(ID,
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DMA_CG_INFO_REG_IDX(0, _DMA_FSM_GROUP_ADDR_B_IDX));
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tmp = dma_reg_load(ID,
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DMA_CG_INFO_REG_IDX(
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_DMA_FSM_GROUP_FSM_CTRL_STATE_IDX,
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_DMA_FSM_GROUP_FSM_CTRL_IDX));
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state->fsm_ctrl_idle = tmp & 0x1;
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state->fsm_ctrl_run = tmp & 0x2;
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state->fsm_ctrl_stalling = tmp & 0x4;
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state->fsm_ctrl_error = tmp & 0x8;
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tmp = tmp >> 4;
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/* state->fsm_ctrl_state = (dma_ctrl_states_t)tmp; */
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if (tmp == 0)
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state->fsm_ctrl_state = DMA_CTRL_STATE_IDLE;
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if (tmp == 1)
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state->fsm_ctrl_state = DMA_CTRL_STATE_REQ_RCV;
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if (tmp == 2)
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state->fsm_ctrl_state = DMA_CTRL_STATE_RCV;
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if (tmp == 3)
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state->fsm_ctrl_state = DMA_CTRL_STATE_RCV_REQ;
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if (tmp == 4)
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state->fsm_ctrl_state = DMA_CTRL_STATE_INIT;
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state->fsm_ctrl_source_dev = dma_reg_load(ID,
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DMA_CG_INFO_REG_IDX(
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_DMA_FSM_GROUP_FSM_CTRL_REQ_DEV_IDX,
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_DMA_FSM_GROUP_FSM_CTRL_IDX));
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state->fsm_ctrl_source_addr = dma_reg_load(ID,
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DMA_CG_INFO_REG_IDX(
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_DMA_FSM_GROUP_FSM_CTRL_REQ_ADDR_IDX,
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_DMA_FSM_GROUP_FSM_CTRL_IDX));
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state->fsm_ctrl_source_stride = dma_reg_load(ID,
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DMA_CG_INFO_REG_IDX(
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_DMA_FSM_GROUP_FSM_CTRL_REQ_STRIDE_IDX,
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_DMA_FSM_GROUP_FSM_CTRL_IDX));
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state->fsm_ctrl_source_width = dma_reg_load(ID,
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DMA_CG_INFO_REG_IDX(
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_DMA_FSM_GROUP_FSM_CTRL_REQ_XB_IDX,
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_DMA_FSM_GROUP_FSM_CTRL_IDX));
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state->fsm_ctrl_source_height = dma_reg_load(ID,
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DMA_CG_INFO_REG_IDX(
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_DMA_FSM_GROUP_FSM_CTRL_REQ_YB_IDX,
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_DMA_FSM_GROUP_FSM_CTRL_IDX));
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state->fsm_ctrl_pack_source_dev = dma_reg_load(ID,
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DMA_CG_INFO_REG_IDX(
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_DMA_FSM_GROUP_FSM_CTRL_PACK_REQ_DEV_IDX,
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_DMA_FSM_GROUP_FSM_CTRL_IDX));
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state->fsm_ctrl_pack_dest_dev = dma_reg_load(ID,
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DMA_CG_INFO_REG_IDX(
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_DMA_FSM_GROUP_FSM_CTRL_PACK_WR_DEV_IDX,
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_DMA_FSM_GROUP_FSM_CTRL_IDX));
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state->fsm_ctrl_dest_addr = dma_reg_load(ID,
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DMA_CG_INFO_REG_IDX(
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_DMA_FSM_GROUP_FSM_CTRL_WR_ADDR_IDX,
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_DMA_FSM_GROUP_FSM_CTRL_IDX));
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state->fsm_ctrl_dest_stride = dma_reg_load(ID,
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DMA_CG_INFO_REG_IDX(
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_DMA_FSM_GROUP_FSM_CTRL_WR_STRIDE_IDX,
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_DMA_FSM_GROUP_FSM_CTRL_IDX));
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state->fsm_ctrl_pack_source_width = dma_reg_load(ID,
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DMA_CG_INFO_REG_IDX(
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_DMA_FSM_GROUP_FSM_CTRL_PACK_REQ_XB_IDX,
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_DMA_FSM_GROUP_FSM_CTRL_IDX));
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state->fsm_ctrl_pack_dest_height = dma_reg_load(ID,
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DMA_CG_INFO_REG_IDX(
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_DMA_FSM_GROUP_FSM_CTRL_PACK_WR_YB_IDX,
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_DMA_FSM_GROUP_FSM_CTRL_IDX));
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state->fsm_ctrl_pack_dest_width = dma_reg_load(ID,
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DMA_CG_INFO_REG_IDX(
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_DMA_FSM_GROUP_FSM_CTRL_PACK_WR_XB_IDX,
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_DMA_FSM_GROUP_FSM_CTRL_IDX));
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state->fsm_ctrl_pack_source_elems = dma_reg_load(ID,
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DMA_CG_INFO_REG_IDX(
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_DMA_FSM_GROUP_FSM_CTRL_PACK_ELEM_REQ_IDX,
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_DMA_FSM_GROUP_FSM_CTRL_IDX));
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state->fsm_ctrl_pack_dest_elems = dma_reg_load(ID,
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DMA_CG_INFO_REG_IDX(
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_DMA_FSM_GROUP_FSM_CTRL_PACK_ELEM_WR_IDX,
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_DMA_FSM_GROUP_FSM_CTRL_IDX));
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state->fsm_ctrl_pack_extension = dma_reg_load(ID,
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DMA_CG_INFO_REG_IDX(
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_DMA_FSM_GROUP_FSM_CTRL_PACK_S_Z_IDX,
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_DMA_FSM_GROUP_FSM_CTRL_IDX));
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tmp = dma_reg_load(ID,
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DMA_CG_INFO_REG_IDX(
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_DMA_FSM_GROUP_FSM_PACK_STATE_IDX,
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_DMA_FSM_GROUP_FSM_PACK_IDX));
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state->pack_idle = tmp & 0x1;
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state->pack_run = tmp & 0x2;
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state->pack_stalling = tmp & 0x4;
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state->pack_error = tmp & 0x8;
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state->pack_cnt_height = dma_reg_load(ID,
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DMA_CG_INFO_REG_IDX(
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_DMA_FSM_GROUP_FSM_PACK_CNT_YB_IDX,
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_DMA_FSM_GROUP_FSM_PACK_IDX));
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state->pack_src_cnt_width = dma_reg_load(ID,
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DMA_CG_INFO_REG_IDX(
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_DMA_FSM_GROUP_FSM_PACK_CNT_XB_REQ_IDX,
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_DMA_FSM_GROUP_FSM_PACK_IDX));
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state->pack_dest_cnt_width = dma_reg_load(ID,
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DMA_CG_INFO_REG_IDX(
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_DMA_FSM_GROUP_FSM_PACK_CNT_XB_WR_IDX,
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_DMA_FSM_GROUP_FSM_PACK_IDX));
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tmp = dma_reg_load(ID,
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DMA_CG_INFO_REG_IDX(
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_DMA_FSM_GROUP_FSM_REQ_STATE_IDX,
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_DMA_FSM_GROUP_FSM_REQ_IDX));
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/* state->read_state = (dma_rw_states_t)tmp; */
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if (tmp == 0)
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state->read_state = DMA_RW_STATE_IDLE;
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if (tmp == 1)
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state->read_state = DMA_RW_STATE_REQ;
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if (tmp == 2)
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state->read_state = DMA_RW_STATE_NEXT_LINE;
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if (tmp == 3)
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state->read_state = DMA_RW_STATE_UNLOCK_CHANNEL;
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state->read_cnt_height = dma_reg_load(ID,
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DMA_CG_INFO_REG_IDX(
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_DMA_FSM_GROUP_FSM_REQ_CNT_YB_IDX,
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_DMA_FSM_GROUP_FSM_REQ_IDX));
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state->read_cnt_width = dma_reg_load(ID,
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DMA_CG_INFO_REG_IDX(
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_DMA_FSM_GROUP_FSM_REQ_CNT_XB_IDX,
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_DMA_FSM_GROUP_FSM_REQ_IDX));
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tmp = dma_reg_load(ID,
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DMA_CG_INFO_REG_IDX(
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_DMA_FSM_GROUP_FSM_WR_STATE_IDX,
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_DMA_FSM_GROUP_FSM_WR_IDX));
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/* state->write_state = (dma_rw_states_t)tmp; */
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if (tmp == 0)
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state->write_state = DMA_RW_STATE_IDLE;
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if (tmp == 1)
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state->write_state = DMA_RW_STATE_REQ;
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if (tmp == 2)
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state->write_state = DMA_RW_STATE_NEXT_LINE;
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if (tmp == 3)
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state->write_state = DMA_RW_STATE_UNLOCK_CHANNEL;
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state->write_height = dma_reg_load(ID,
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DMA_CG_INFO_REG_IDX(
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_DMA_FSM_GROUP_FSM_WR_CNT_YB_IDX,
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_DMA_FSM_GROUP_FSM_WR_IDX));
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state->write_width = dma_reg_load(ID,
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DMA_CG_INFO_REG_IDX(
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_DMA_FSM_GROUP_FSM_WR_CNT_XB_IDX,
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_DMA_FSM_GROUP_FSM_WR_IDX));
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for (i = 0; i < HIVE_ISP_NUM_DMA_CONNS; i++) {
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dma_port_state_t *port = &state->port_states[i];
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tmp = dma_reg_load(ID, DMA_DEV_INFO_REG_IDX(0, i));
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port->req_cs = ((tmp & 0x1) != 0);
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port->req_we_n = ((tmp & 0x2) != 0);
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port->req_run = ((tmp & 0x4) != 0);
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port->req_ack = ((tmp & 0x8) != 0);
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tmp = dma_reg_load(ID, DMA_DEV_INFO_REG_IDX(1, i));
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port->send_cs = ((tmp & 0x1) != 0);
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port->send_we_n = ((tmp & 0x2) != 0);
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port->send_run = ((tmp & 0x4) != 0);
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port->send_ack = ((tmp & 0x8) != 0);
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tmp = dma_reg_load(ID, DMA_DEV_INFO_REG_IDX(2, i));
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if (tmp & 0x1)
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port->fifo_state = DMA_FIFO_STATE_WILL_BE_FULL;
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if (tmp & 0x2)
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port->fifo_state = DMA_FIFO_STATE_FULL;
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if (tmp & 0x4)
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port->fifo_state = DMA_FIFO_STATE_EMPTY;
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port->fifo_counter = tmp >> 3;
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}
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for (i = 0; i < HIVE_DMA_NUM_CHANNELS; i++) {
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dma_channel_state_t *ch = &state->channel_states[i];
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ch->connection = DMA_GET_CONNECTION(dma_reg_load(ID,
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DMA_CHANNEL_PARAM_REG_IDX(i,
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_DMA_PACKING_SETUP_PARAM)));
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ch->sign_extend = DMA_GET_EXTENSION(dma_reg_load(ID,
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DMA_CHANNEL_PARAM_REG_IDX(i,
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_DMA_PACKING_SETUP_PARAM)));
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ch->height = dma_reg_load(ID,
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DMA_CHANNEL_PARAM_REG_IDX(i,
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_DMA_HEIGHT_PARAM));
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ch->stride_a = dma_reg_load(ID,
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DMA_CHANNEL_PARAM_REG_IDX(i,
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_DMA_STRIDE_A_PARAM));
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ch->elems_a = DMA_GET_ELEMENTS(dma_reg_load(ID,
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DMA_CHANNEL_PARAM_REG_IDX(i,
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_DMA_ELEM_CROPPING_A_PARAM)));
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ch->cropping_a = DMA_GET_CROPPING(dma_reg_load(ID,
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DMA_CHANNEL_PARAM_REG_IDX(i,
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_DMA_ELEM_CROPPING_A_PARAM)));
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ch->width_a = dma_reg_load(ID,
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DMA_CHANNEL_PARAM_REG_IDX(i,
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_DMA_WIDTH_A_PARAM));
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ch->stride_b = dma_reg_load(ID,
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DMA_CHANNEL_PARAM_REG_IDX(i,
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_DMA_STRIDE_B_PARAM));
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ch->elems_b = DMA_GET_ELEMENTS(dma_reg_load(ID,
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DMA_CHANNEL_PARAM_REG_IDX(i,
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_DMA_ELEM_CROPPING_B_PARAM)));
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ch->cropping_b = DMA_GET_CROPPING(dma_reg_load(ID,
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DMA_CHANNEL_PARAM_REG_IDX(i,
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_DMA_ELEM_CROPPING_B_PARAM)));
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ch->width_b = dma_reg_load(ID,
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DMA_CHANNEL_PARAM_REG_IDX(i,
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_DMA_WIDTH_B_PARAM));
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}
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}
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void
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dma_set_max_burst_size(const dma_ID_t ID, dma_connection conn,
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uint32_t max_burst_size)
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{
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assert(ID < N_DMA_ID);
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assert(max_burst_size > 0);
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dma_reg_store(ID, DMA_DEV_INFO_REG_IDX(_DMA_DEV_INTERF_MAX_BURST_IDX, conn),
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max_burst_size - 1);
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}
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