/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2016-2018 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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/************************************
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** This is an auto-generated file **
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** DO NOT EDIT BELOW **
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************************************/
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#ifndef ASIC_REG_DMA_CH_1_REGS_H_
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#define ASIC_REG_DMA_CH_1_REGS_H_
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/*
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*****************************************
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* DMA_CH_1 (Prototype: DMA_CH)
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*****************************************
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*/
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#define mmDMA_CH_1_CFG0 0x409000
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#define mmDMA_CH_1_CFG1 0x409004
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#define mmDMA_CH_1_ERRMSG_ADDR_LO 0x409008
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#define mmDMA_CH_1_ERRMSG_ADDR_HI 0x40900C
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#define mmDMA_CH_1_ERRMSG_WDATA 0x409010
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#define mmDMA_CH_1_RD_COMP_ADDR_LO 0x409014
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#define mmDMA_CH_1_RD_COMP_ADDR_HI 0x409018
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#define mmDMA_CH_1_RD_COMP_WDATA 0x40901C
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#define mmDMA_CH_1_WR_COMP_ADDR_LO 0x409020
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#define mmDMA_CH_1_WR_COMP_ADDR_HI 0x409024
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#define mmDMA_CH_1_WR_COMP_WDATA 0x409028
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#define mmDMA_CH_1_LDMA_SRC_ADDR_LO 0x40902C
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#define mmDMA_CH_1_LDMA_SRC_ADDR_HI 0x409030
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#define mmDMA_CH_1_LDMA_DST_ADDR_LO 0x409034
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#define mmDMA_CH_1_LDMA_DST_ADDR_HI 0x409038
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#define mmDMA_CH_1_LDMA_TSIZE 0x40903C
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#define mmDMA_CH_1_COMIT_TRANSFER 0x409040
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#define mmDMA_CH_1_STS0 0x409044
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#define mmDMA_CH_1_STS1 0x409048
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#define mmDMA_CH_1_STS2 0x40904C
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#define mmDMA_CH_1_STS3 0x409050
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#define mmDMA_CH_1_STS4 0x409054
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#define mmDMA_CH_1_SRC_ADDR_LO_STS 0x409058
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#define mmDMA_CH_1_SRC_ADDR_HI_STS 0x40905C
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#define mmDMA_CH_1_SRC_TSIZE_STS 0x409060
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#define mmDMA_CH_1_DST_ADDR_LO_STS 0x409064
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#define mmDMA_CH_1_DST_ADDR_HI_STS 0x409068
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#define mmDMA_CH_1_DST_TSIZE_STS 0x40906C
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#define mmDMA_CH_1_RD_RATE_LIM_EN 0x409070
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#define mmDMA_CH_1_RD_RATE_LIM_RST_TOKEN 0x409074
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#define mmDMA_CH_1_RD_RATE_LIM_SAT 0x409078
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#define mmDMA_CH_1_RD_RATE_LIM_TOUT 0x40907C
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#define mmDMA_CH_1_WR_RATE_LIM_EN 0x409080
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#define mmDMA_CH_1_WR_RATE_LIM_RST_TOKEN 0x409084
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#define mmDMA_CH_1_WR_RATE_LIM_SAT 0x409088
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#define mmDMA_CH_1_WR_RATE_LIM_TOUT 0x40908C
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#define mmDMA_CH_1_CFG2 0x409090
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#define mmDMA_CH_1_TDMA_CTL 0x409100
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#define mmDMA_CH_1_TDMA_SRC_BASE_ADDR_LO 0x409104
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#define mmDMA_CH_1_TDMA_SRC_BASE_ADDR_HI 0x409108
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#define mmDMA_CH_1_TDMA_SRC_ROI_BASE_0 0x40910C
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#define mmDMA_CH_1_TDMA_SRC_ROI_SIZE_0 0x409110
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#define mmDMA_CH_1_TDMA_SRC_VALID_ELEMENTS_0 0x409114
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#define mmDMA_CH_1_TDMA_SRC_START_OFFSET_0 0x409118
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#define mmDMA_CH_1_TDMA_SRC_STRIDE_0 0x40911C
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#define mmDMA_CH_1_TDMA_SRC_ROI_BASE_1 0x409120
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#define mmDMA_CH_1_TDMA_SRC_ROI_SIZE_1 0x409124
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#define mmDMA_CH_1_TDMA_SRC_VALID_ELEMENTS_1 0x409128
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#define mmDMA_CH_1_TDMA_SRC_START_OFFSET_1 0x40912C
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#define mmDMA_CH_1_TDMA_SRC_STRIDE_1 0x409130
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#define mmDMA_CH_1_TDMA_SRC_ROI_BASE_2 0x409134
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#define mmDMA_CH_1_TDMA_SRC_ROI_SIZE_2 0x409138
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#define mmDMA_CH_1_TDMA_SRC_VALID_ELEMENTS_2 0x40913C
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#define mmDMA_CH_1_TDMA_SRC_START_OFFSET_2 0x409140
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#define mmDMA_CH_1_TDMA_SRC_STRIDE_2 0x409144
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#define mmDMA_CH_1_TDMA_SRC_ROI_BASE_3 0x409148
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#define mmDMA_CH_1_TDMA_SRC_ROI_SIZE_3 0x40914C
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#define mmDMA_CH_1_TDMA_SRC_VALID_ELEMENTS_3 0x409150
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#define mmDMA_CH_1_TDMA_SRC_START_OFFSET_3 0x409154
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#define mmDMA_CH_1_TDMA_SRC_STRIDE_3 0x409158
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#define mmDMA_CH_1_TDMA_SRC_ROI_BASE_4 0x40915C
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#define mmDMA_CH_1_TDMA_SRC_ROI_SIZE_4 0x409160
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#define mmDMA_CH_1_TDMA_SRC_VALID_ELEMENTS_4 0x409164
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#define mmDMA_CH_1_TDMA_SRC_START_OFFSET_4 0x409168
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#define mmDMA_CH_1_TDMA_SRC_STRIDE_4 0x40916C
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#define mmDMA_CH_1_TDMA_DST_BASE_ADDR_LO 0x409170
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#define mmDMA_CH_1_TDMA_DST_BASE_ADDR_HI 0x409174
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#define mmDMA_CH_1_TDMA_DST_ROI_BASE_0 0x409178
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#define mmDMA_CH_1_TDMA_DST_ROI_SIZE_0 0x40917C
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#define mmDMA_CH_1_TDMA_DST_VALID_ELEMENTS_0 0x409180
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#define mmDMA_CH_1_TDMA_DST_START_OFFSET_0 0x409184
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#define mmDMA_CH_1_TDMA_DST_STRIDE_0 0x409188
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#define mmDMA_CH_1_TDMA_DST_ROI_BASE_1 0x40918C
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#define mmDMA_CH_1_TDMA_DST_ROI_SIZE_1 0x409190
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#define mmDMA_CH_1_TDMA_DST_VALID_ELEMENTS_1 0x409194
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#define mmDMA_CH_1_TDMA_DST_START_OFFSET_1 0x409198
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#define mmDMA_CH_1_TDMA_DST_STRIDE_1 0x40919C
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#define mmDMA_CH_1_TDMA_DST_ROI_BASE_2 0x4091A0
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#define mmDMA_CH_1_TDMA_DST_ROI_SIZE_2 0x4091A4
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#define mmDMA_CH_1_TDMA_DST_VALID_ELEMENTS_2 0x4091A8
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#define mmDMA_CH_1_TDMA_DST_START_OFFSET_2 0x4091AC
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#define mmDMA_CH_1_TDMA_DST_STRIDE_2 0x4091B0
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#define mmDMA_CH_1_TDMA_DST_ROI_BASE_3 0x4091B4
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#define mmDMA_CH_1_TDMA_DST_ROI_SIZE_3 0x4091B8
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#define mmDMA_CH_1_TDMA_DST_VALID_ELEMENTS_3 0x4091BC
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#define mmDMA_CH_1_TDMA_DST_START_OFFSET_3 0x4091C0
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#define mmDMA_CH_1_TDMA_DST_STRIDE_3 0x4091C4
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#define mmDMA_CH_1_TDMA_DST_ROI_BASE_4 0x4091C8
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#define mmDMA_CH_1_TDMA_DST_ROI_SIZE_4 0x4091CC
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#define mmDMA_CH_1_TDMA_DST_VALID_ELEMENTS_4 0x4091D0
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#define mmDMA_CH_1_TDMA_DST_START_OFFSET_4 0x4091D4
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#define mmDMA_CH_1_TDMA_DST_STRIDE_4 0x4091D8
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#define mmDMA_CH_1_MEM_INIT_BUSY 0x4091FC
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#endif /* ASIC_REG_DMA_CH_1_REGS_H_ */
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