/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2016-2018 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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/************************************
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** This is an auto-generated file **
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** DO NOT EDIT BELOW **
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************************************/
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#ifndef ASIC_REG_DMA4_QM_REGS_H_
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#define ASIC_REG_DMA4_QM_REGS_H_
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/*
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*****************************************
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* DMA4_QM (Prototype: QMAN)
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*****************************************
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*/
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#define mmDMA4_QM_GLBL_CFG0 0x588000
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#define mmDMA4_QM_GLBL_CFG1 0x588004
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#define mmDMA4_QM_GLBL_PROT 0x588008
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#define mmDMA4_QM_GLBL_ERR_CFG 0x58800C
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#define mmDMA4_QM_GLBL_SECURE_PROPS_0 0x588010
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#define mmDMA4_QM_GLBL_SECURE_PROPS_1 0x588014
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#define mmDMA4_QM_GLBL_SECURE_PROPS_2 0x588018
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#define mmDMA4_QM_GLBL_SECURE_PROPS_3 0x58801C
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#define mmDMA4_QM_GLBL_SECURE_PROPS_4 0x588020
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#define mmDMA4_QM_GLBL_NON_SECURE_PROPS_0 0x588024
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#define mmDMA4_QM_GLBL_NON_SECURE_PROPS_1 0x588028
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#define mmDMA4_QM_GLBL_NON_SECURE_PROPS_2 0x58802C
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#define mmDMA4_QM_GLBL_NON_SECURE_PROPS_3 0x588030
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#define mmDMA4_QM_GLBL_NON_SECURE_PROPS_4 0x588034
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#define mmDMA4_QM_GLBL_STS0 0x588038
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#define mmDMA4_QM_GLBL_STS1_0 0x588040
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#define mmDMA4_QM_GLBL_STS1_1 0x588044
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#define mmDMA4_QM_GLBL_STS1_2 0x588048
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#define mmDMA4_QM_GLBL_STS1_3 0x58804C
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#define mmDMA4_QM_GLBL_STS1_4 0x588050
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#define mmDMA4_QM_GLBL_MSG_EN_0 0x588054
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#define mmDMA4_QM_GLBL_MSG_EN_1 0x588058
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#define mmDMA4_QM_GLBL_MSG_EN_2 0x58805C
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#define mmDMA4_QM_GLBL_MSG_EN_3 0x588060
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#define mmDMA4_QM_GLBL_MSG_EN_4 0x588068
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#define mmDMA4_QM_PQ_BASE_LO_0 0x588070
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#define mmDMA4_QM_PQ_BASE_LO_1 0x588074
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#define mmDMA4_QM_PQ_BASE_LO_2 0x588078
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#define mmDMA4_QM_PQ_BASE_LO_3 0x58807C
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#define mmDMA4_QM_PQ_BASE_HI_0 0x588080
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#define mmDMA4_QM_PQ_BASE_HI_1 0x588084
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#define mmDMA4_QM_PQ_BASE_HI_2 0x588088
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#define mmDMA4_QM_PQ_BASE_HI_3 0x58808C
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#define mmDMA4_QM_PQ_SIZE_0 0x588090
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#define mmDMA4_QM_PQ_SIZE_1 0x588094
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#define mmDMA4_QM_PQ_SIZE_2 0x588098
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#define mmDMA4_QM_PQ_SIZE_3 0x58809C
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#define mmDMA4_QM_PQ_PI_0 0x5880A0
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#define mmDMA4_QM_PQ_PI_1 0x5880A4
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#define mmDMA4_QM_PQ_PI_2 0x5880A8
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#define mmDMA4_QM_PQ_PI_3 0x5880AC
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#define mmDMA4_QM_PQ_CI_0 0x5880B0
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#define mmDMA4_QM_PQ_CI_1 0x5880B4
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#define mmDMA4_QM_PQ_CI_2 0x5880B8
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#define mmDMA4_QM_PQ_CI_3 0x5880BC
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#define mmDMA4_QM_PQ_CFG0_0 0x5880C0
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#define mmDMA4_QM_PQ_CFG0_1 0x5880C4
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#define mmDMA4_QM_PQ_CFG0_2 0x5880C8
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#define mmDMA4_QM_PQ_CFG0_3 0x5880CC
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#define mmDMA4_QM_PQ_CFG1_0 0x5880D0
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#define mmDMA4_QM_PQ_CFG1_1 0x5880D4
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#define mmDMA4_QM_PQ_CFG1_2 0x5880D8
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#define mmDMA4_QM_PQ_CFG1_3 0x5880DC
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#define mmDMA4_QM_PQ_ARUSER_31_11_0 0x5880E0
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#define mmDMA4_QM_PQ_ARUSER_31_11_1 0x5880E4
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#define mmDMA4_QM_PQ_ARUSER_31_11_2 0x5880E8
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#define mmDMA4_QM_PQ_ARUSER_31_11_3 0x5880EC
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#define mmDMA4_QM_PQ_STS0_0 0x5880F0
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#define mmDMA4_QM_PQ_STS0_1 0x5880F4
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#define mmDMA4_QM_PQ_STS0_2 0x5880F8
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#define mmDMA4_QM_PQ_STS0_3 0x5880FC
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#define mmDMA4_QM_PQ_STS1_0 0x588100
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#define mmDMA4_QM_PQ_STS1_1 0x588104
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#define mmDMA4_QM_PQ_STS1_2 0x588108
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#define mmDMA4_QM_PQ_STS1_3 0x58810C
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#define mmDMA4_QM_CQ_CFG0_0 0x588110
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#define mmDMA4_QM_CQ_CFG0_1 0x588114
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#define mmDMA4_QM_CQ_CFG0_2 0x588118
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#define mmDMA4_QM_CQ_CFG0_3 0x58811C
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#define mmDMA4_QM_CQ_CFG0_4 0x588120
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#define mmDMA4_QM_CQ_CFG1_0 0x588124
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#define mmDMA4_QM_CQ_CFG1_1 0x588128
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#define mmDMA4_QM_CQ_CFG1_2 0x58812C
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#define mmDMA4_QM_CQ_CFG1_3 0x588130
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#define mmDMA4_QM_CQ_CFG1_4 0x588134
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#define mmDMA4_QM_CQ_ARUSER_31_11_0 0x588138
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#define mmDMA4_QM_CQ_ARUSER_31_11_1 0x58813C
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#define mmDMA4_QM_CQ_ARUSER_31_11_2 0x588140
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#define mmDMA4_QM_CQ_ARUSER_31_11_3 0x588144
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#define mmDMA4_QM_CQ_ARUSER_31_11_4 0x588148
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#define mmDMA4_QM_CQ_STS0_0 0x58814C
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#define mmDMA4_QM_CQ_STS0_1 0x588150
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#define mmDMA4_QM_CQ_STS0_2 0x588154
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#define mmDMA4_QM_CQ_STS0_3 0x588158
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#define mmDMA4_QM_CQ_STS0_4 0x58815C
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#define mmDMA4_QM_CQ_STS1_0 0x588160
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#define mmDMA4_QM_CQ_STS1_1 0x588164
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#define mmDMA4_QM_CQ_STS1_2 0x588168
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#define mmDMA4_QM_CQ_STS1_3 0x58816C
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#define mmDMA4_QM_CQ_STS1_4 0x588170
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#define mmDMA4_QM_CQ_PTR_LO_0 0x588174
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#define mmDMA4_QM_CQ_PTR_HI_0 0x588178
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#define mmDMA4_QM_CQ_TSIZE_0 0x58817C
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#define mmDMA4_QM_CQ_CTL_0 0x588180
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#define mmDMA4_QM_CQ_PTR_LO_1 0x588184
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#define mmDMA4_QM_CQ_PTR_HI_1 0x588188
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#define mmDMA4_QM_CQ_TSIZE_1 0x58818C
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#define mmDMA4_QM_CQ_CTL_1 0x588190
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#define mmDMA4_QM_CQ_PTR_LO_2 0x588194
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#define mmDMA4_QM_CQ_PTR_HI_2 0x588198
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#define mmDMA4_QM_CQ_TSIZE_2 0x58819C
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#define mmDMA4_QM_CQ_CTL_2 0x5881A0
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#define mmDMA4_QM_CQ_PTR_LO_3 0x5881A4
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#define mmDMA4_QM_CQ_PTR_HI_3 0x5881A8
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#define mmDMA4_QM_CQ_TSIZE_3 0x5881AC
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#define mmDMA4_QM_CQ_CTL_3 0x5881B0
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#define mmDMA4_QM_CQ_PTR_LO_4 0x5881B4
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#define mmDMA4_QM_CQ_PTR_HI_4 0x5881B8
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#define mmDMA4_QM_CQ_TSIZE_4 0x5881BC
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#define mmDMA4_QM_CQ_CTL_4 0x5881C0
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#define mmDMA4_QM_CQ_PTR_LO_STS_0 0x5881C4
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#define mmDMA4_QM_CQ_PTR_LO_STS_1 0x5881C8
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#define mmDMA4_QM_CQ_PTR_LO_STS_2 0x5881CC
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#define mmDMA4_QM_CQ_PTR_LO_STS_3 0x5881D0
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#define mmDMA4_QM_CQ_PTR_LO_STS_4 0x5881D4
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#define mmDMA4_QM_CQ_PTR_HI_STS_0 0x5881D8
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#define mmDMA4_QM_CQ_PTR_HI_STS_1 0x5881DC
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#define mmDMA4_QM_CQ_PTR_HI_STS_2 0x5881E0
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#define mmDMA4_QM_CQ_PTR_HI_STS_3 0x5881E4
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#define mmDMA4_QM_CQ_PTR_HI_STS_4 0x5881E8
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#define mmDMA4_QM_CQ_TSIZE_STS_0 0x5881EC
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#define mmDMA4_QM_CQ_TSIZE_STS_1 0x5881F0
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#define mmDMA4_QM_CQ_TSIZE_STS_2 0x5881F4
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#define mmDMA4_QM_CQ_TSIZE_STS_3 0x5881F8
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#define mmDMA4_QM_CQ_TSIZE_STS_4 0x5881FC
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#define mmDMA4_QM_CQ_CTL_STS_0 0x588200
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#define mmDMA4_QM_CQ_CTL_STS_1 0x588204
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#define mmDMA4_QM_CQ_CTL_STS_2 0x588208
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#define mmDMA4_QM_CQ_CTL_STS_3 0x58820C
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#define mmDMA4_QM_CQ_CTL_STS_4 0x588210
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#define mmDMA4_QM_CQ_IFIFO_CNT_0 0x588214
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#define mmDMA4_QM_CQ_IFIFO_CNT_1 0x588218
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#define mmDMA4_QM_CQ_IFIFO_CNT_2 0x58821C
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#define mmDMA4_QM_CQ_IFIFO_CNT_3 0x588220
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#define mmDMA4_QM_CQ_IFIFO_CNT_4 0x588224
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#define mmDMA4_QM_CP_MSG_BASE0_ADDR_LO_0 0x588228
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#define mmDMA4_QM_CP_MSG_BASE0_ADDR_LO_1 0x58822C
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#define mmDMA4_QM_CP_MSG_BASE0_ADDR_LO_2 0x588230
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#define mmDMA4_QM_CP_MSG_BASE0_ADDR_LO_3 0x588234
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#define mmDMA4_QM_CP_MSG_BASE0_ADDR_LO_4 0x588238
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#define mmDMA4_QM_CP_MSG_BASE0_ADDR_HI_0 0x58823C
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#define mmDMA4_QM_CP_MSG_BASE0_ADDR_HI_1 0x588240
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#define mmDMA4_QM_CP_MSG_BASE0_ADDR_HI_2 0x588244
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#define mmDMA4_QM_CP_MSG_BASE0_ADDR_HI_3 0x588248
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#define mmDMA4_QM_CP_MSG_BASE0_ADDR_HI_4 0x58824C
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#define mmDMA4_QM_CP_MSG_BASE1_ADDR_LO_0 0x588250
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#define mmDMA4_QM_CP_MSG_BASE1_ADDR_LO_1 0x588254
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#define mmDMA4_QM_CP_MSG_BASE1_ADDR_LO_2 0x588258
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#define mmDMA4_QM_CP_MSG_BASE1_ADDR_LO_3 0x58825C
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#define mmDMA4_QM_CP_MSG_BASE1_ADDR_LO_4 0x588260
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#define mmDMA4_QM_CP_MSG_BASE1_ADDR_HI_0 0x588264
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#define mmDMA4_QM_CP_MSG_BASE1_ADDR_HI_1 0x588268
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#define mmDMA4_QM_CP_MSG_BASE1_ADDR_HI_2 0x58826C
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#define mmDMA4_QM_CP_MSG_BASE1_ADDR_HI_3 0x588270
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#define mmDMA4_QM_CP_MSG_BASE1_ADDR_HI_4 0x588274
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#define mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_0 0x588278
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#define mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_1 0x58827C
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#define mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_2 0x588280
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#define mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_3 0x588284
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#define mmDMA4_QM_CP_MSG_BASE2_ADDR_LO_4 0x588288
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#define mmDMA4_QM_CP_MSG_BASE2_ADDR_HI_0 0x58828C
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#define mmDMA4_QM_CP_MSG_BASE2_ADDR_HI_1 0x588290
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#define mmDMA4_QM_CP_MSG_BASE2_ADDR_HI_2 0x588294
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#define mmDMA4_QM_CP_MSG_BASE2_ADDR_HI_3 0x588298
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#define mmDMA4_QM_CP_MSG_BASE2_ADDR_HI_4 0x58829C
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#define mmDMA4_QM_CP_MSG_BASE3_ADDR_LO_0 0x5882A0
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#define mmDMA4_QM_CP_MSG_BASE3_ADDR_LO_1 0x5882A4
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#define mmDMA4_QM_CP_MSG_BASE3_ADDR_LO_2 0x5882A8
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#define mmDMA4_QM_CP_MSG_BASE3_ADDR_LO_3 0x5882AC
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#define mmDMA4_QM_CP_MSG_BASE3_ADDR_LO_4 0x5882B0
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#define mmDMA4_QM_CP_MSG_BASE3_ADDR_HI_0 0x5882B4
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#define mmDMA4_QM_CP_MSG_BASE3_ADDR_HI_1 0x5882B8
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#define mmDMA4_QM_CP_MSG_BASE3_ADDR_HI_2 0x5882BC
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#define mmDMA4_QM_CP_MSG_BASE3_ADDR_HI_3 0x5882C0
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#define mmDMA4_QM_CP_MSG_BASE3_ADDR_HI_4 0x5882C4
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#define mmDMA4_QM_CP_LDMA_TSIZE_OFFSET_0 0x5882C8
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#define mmDMA4_QM_CP_LDMA_TSIZE_OFFSET_1 0x5882CC
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#define mmDMA4_QM_CP_LDMA_TSIZE_OFFSET_2 0x5882D0
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#define mmDMA4_QM_CP_LDMA_TSIZE_OFFSET_3 0x5882D4
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#define mmDMA4_QM_CP_LDMA_TSIZE_OFFSET_4 0x5882D8
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#define mmDMA4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0x5882E0
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#define mmDMA4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0x5882E4
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#define mmDMA4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0x5882E8
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#define mmDMA4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0x5882EC
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#define mmDMA4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0x5882F0
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#define mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0x5882F4
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#define mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0x5882F8
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#define mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0x5882FC
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#define mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0x588300
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#define mmDMA4_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0x588304
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#define mmDMA4_QM_CP_FENCE0_RDATA_0 0x588308
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#define mmDMA4_QM_CP_FENCE0_RDATA_1 0x58830C
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#define mmDMA4_QM_CP_FENCE0_RDATA_2 0x588310
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#define mmDMA4_QM_CP_FENCE0_RDATA_3 0x588314
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#define mmDMA4_QM_CP_FENCE0_RDATA_4 0x588318
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#define mmDMA4_QM_CP_FENCE1_RDATA_0 0x58831C
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#define mmDMA4_QM_CP_FENCE1_RDATA_1 0x588320
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#define mmDMA4_QM_CP_FENCE1_RDATA_2 0x588324
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#define mmDMA4_QM_CP_FENCE1_RDATA_3 0x588328
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#define mmDMA4_QM_CP_FENCE1_RDATA_4 0x58832C
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#define mmDMA4_QM_CP_FENCE2_RDATA_0 0x588330
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#define mmDMA4_QM_CP_FENCE2_RDATA_1 0x588334
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#define mmDMA4_QM_CP_FENCE2_RDATA_2 0x588338
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#define mmDMA4_QM_CP_FENCE2_RDATA_3 0x58833C
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#define mmDMA4_QM_CP_FENCE2_RDATA_4 0x588340
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#define mmDMA4_QM_CP_FENCE3_RDATA_0 0x588344
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#define mmDMA4_QM_CP_FENCE3_RDATA_1 0x588348
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#define mmDMA4_QM_CP_FENCE3_RDATA_2 0x58834C
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#define mmDMA4_QM_CP_FENCE3_RDATA_3 0x588350
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#define mmDMA4_QM_CP_FENCE3_RDATA_4 0x588354
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#define mmDMA4_QM_CP_FENCE0_CNT_0 0x588358
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#define mmDMA4_QM_CP_FENCE0_CNT_1 0x58835C
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#define mmDMA4_QM_CP_FENCE0_CNT_2 0x588360
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#define mmDMA4_QM_CP_FENCE0_CNT_3 0x588364
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#define mmDMA4_QM_CP_FENCE0_CNT_4 0x588368
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#define mmDMA4_QM_CP_FENCE1_CNT_0 0x58836C
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#define mmDMA4_QM_CP_FENCE1_CNT_1 0x588370
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#define mmDMA4_QM_CP_FENCE1_CNT_2 0x588374
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#define mmDMA4_QM_CP_FENCE1_CNT_3 0x588378
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#define mmDMA4_QM_CP_FENCE1_CNT_4 0x58837C
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#define mmDMA4_QM_CP_FENCE2_CNT_0 0x588380
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#define mmDMA4_QM_CP_FENCE2_CNT_1 0x588384
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#define mmDMA4_QM_CP_FENCE2_CNT_2 0x588388
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#define mmDMA4_QM_CP_FENCE2_CNT_3 0x58838C
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#define mmDMA4_QM_CP_FENCE2_CNT_4 0x588390
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#define mmDMA4_QM_CP_FENCE3_CNT_0 0x588394
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#define mmDMA4_QM_CP_FENCE3_CNT_1 0x588398
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#define mmDMA4_QM_CP_FENCE3_CNT_2 0x58839C
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#define mmDMA4_QM_CP_FENCE3_CNT_3 0x5883A0
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#define mmDMA4_QM_CP_FENCE3_CNT_4 0x5883A4
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#define mmDMA4_QM_CP_STS_0 0x5883A8
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#define mmDMA4_QM_CP_STS_1 0x5883AC
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#define mmDMA4_QM_CP_STS_2 0x5883B0
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#define mmDMA4_QM_CP_STS_3 0x5883B4
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#define mmDMA4_QM_CP_STS_4 0x5883B8
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#define mmDMA4_QM_CP_CURRENT_INST_LO_0 0x5883BC
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#define mmDMA4_QM_CP_CURRENT_INST_LO_1 0x5883C0
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#define mmDMA4_QM_CP_CURRENT_INST_LO_2 0x5883C4
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#define mmDMA4_QM_CP_CURRENT_INST_LO_3 0x5883C8
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#define mmDMA4_QM_CP_CURRENT_INST_LO_4 0x5883CC
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#define mmDMA4_QM_CP_CURRENT_INST_HI_0 0x5883D0
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#define mmDMA4_QM_CP_CURRENT_INST_HI_1 0x5883D4
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#define mmDMA4_QM_CP_CURRENT_INST_HI_2 0x5883D8
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#define mmDMA4_QM_CP_CURRENT_INST_HI_3 0x5883DC
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#define mmDMA4_QM_CP_CURRENT_INST_HI_4 0x5883E0
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#define mmDMA4_QM_CP_BARRIER_CFG_0 0x5883F4
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#define mmDMA4_QM_CP_BARRIER_CFG_1 0x5883F8
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#define mmDMA4_QM_CP_BARRIER_CFG_2 0x5883FC
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#define mmDMA4_QM_CP_BARRIER_CFG_3 0x588400
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#define mmDMA4_QM_CP_BARRIER_CFG_4 0x588404
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#define mmDMA4_QM_CP_DBG_0_0 0x588408
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#define mmDMA4_QM_CP_DBG_0_1 0x58840C
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#define mmDMA4_QM_CP_DBG_0_2 0x588410
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#define mmDMA4_QM_CP_DBG_0_3 0x588414
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#define mmDMA4_QM_CP_DBG_0_4 0x588418
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#define mmDMA4_QM_CP_ARUSER_31_11_0 0x58841C
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#define mmDMA4_QM_CP_ARUSER_31_11_1 0x588420
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#define mmDMA4_QM_CP_ARUSER_31_11_2 0x588424
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#define mmDMA4_QM_CP_ARUSER_31_11_3 0x588428
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#define mmDMA4_QM_CP_ARUSER_31_11_4 0x58842C
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#define mmDMA4_QM_CP_AWUSER_31_11_0 0x588430
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#define mmDMA4_QM_CP_AWUSER_31_11_1 0x588434
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#define mmDMA4_QM_CP_AWUSER_31_11_2 0x588438
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#define mmDMA4_QM_CP_AWUSER_31_11_3 0x58843C
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#define mmDMA4_QM_CP_AWUSER_31_11_4 0x588440
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#define mmDMA4_QM_ARB_CFG_0 0x588A00
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#define mmDMA4_QM_ARB_CHOISE_Q_PUSH 0x588A04
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#define mmDMA4_QM_ARB_WRR_WEIGHT_0 0x588A08
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#define mmDMA4_QM_ARB_WRR_WEIGHT_1 0x588A0C
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#define mmDMA4_QM_ARB_WRR_WEIGHT_2 0x588A10
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#define mmDMA4_QM_ARB_WRR_WEIGHT_3 0x588A14
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#define mmDMA4_QM_ARB_CFG_1 0x588A18
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#define mmDMA4_QM_ARB_MST_AVAIL_CRED_0 0x588A20
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#define mmDMA4_QM_ARB_MST_AVAIL_CRED_1 0x588A24
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#define mmDMA4_QM_ARB_MST_AVAIL_CRED_2 0x588A28
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#define mmDMA4_QM_ARB_MST_AVAIL_CRED_3 0x588A2C
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#define mmDMA4_QM_ARB_MST_AVAIL_CRED_4 0x588A30
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#define mmDMA4_QM_ARB_MST_AVAIL_CRED_5 0x588A34
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#define mmDMA4_QM_ARB_MST_AVAIL_CRED_6 0x588A38
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#define mmDMA4_QM_ARB_MST_AVAIL_CRED_7 0x588A3C
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#define mmDMA4_QM_ARB_MST_AVAIL_CRED_8 0x588A40
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#define mmDMA4_QM_ARB_MST_AVAIL_CRED_9 0x588A44
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#define mmDMA4_QM_ARB_MST_AVAIL_CRED_10 0x588A48
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#define mmDMA4_QM_ARB_MST_AVAIL_CRED_11 0x588A4C
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#define mmDMA4_QM_ARB_MST_AVAIL_CRED_12 0x588A50
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#define mmDMA4_QM_ARB_MST_AVAIL_CRED_13 0x588A54
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#define mmDMA4_QM_ARB_MST_AVAIL_CRED_14 0x588A58
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#define mmDMA4_QM_ARB_MST_AVAIL_CRED_15 0x588A5C
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#define mmDMA4_QM_ARB_MST_AVAIL_CRED_16 0x588A60
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#define mmDMA4_QM_ARB_MST_AVAIL_CRED_17 0x588A64
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#define mmDMA4_QM_ARB_MST_AVAIL_CRED_18 0x588A68
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#define mmDMA4_QM_ARB_MST_AVAIL_CRED_19 0x588A6C
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#define mmDMA4_QM_ARB_MST_AVAIL_CRED_20 0x588A70
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#define mmDMA4_QM_ARB_MST_AVAIL_CRED_21 0x588A74
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#define mmDMA4_QM_ARB_MST_AVAIL_CRED_22 0x588A78
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#define mmDMA4_QM_ARB_MST_AVAIL_CRED_23 0x588A7C
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#define mmDMA4_QM_ARB_MST_AVAIL_CRED_24 0x588A80
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#define mmDMA4_QM_ARB_MST_AVAIL_CRED_25 0x588A84
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#define mmDMA4_QM_ARB_MST_AVAIL_CRED_26 0x588A88
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#define mmDMA4_QM_ARB_MST_AVAIL_CRED_27 0x588A8C
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#define mmDMA4_QM_ARB_MST_AVAIL_CRED_28 0x588A90
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#define mmDMA4_QM_ARB_MST_AVAIL_CRED_29 0x588A94
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#define mmDMA4_QM_ARB_MST_AVAIL_CRED_30 0x588A98
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#define mmDMA4_QM_ARB_MST_AVAIL_CRED_31 0x588A9C
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#define mmDMA4_QM_ARB_MST_CRED_INC 0x588AA0
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#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_0 0x588AA4
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#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_1 0x588AA8
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#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_2 0x588AAC
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#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_3 0x588AB0
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#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_4 0x588AB4
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#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_5 0x588AB8
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#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_6 0x588ABC
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#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_7 0x588AC0
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#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_8 0x588AC4
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#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_9 0x588AC8
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#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_10 0x588ACC
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#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_11 0x588AD0
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#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_12 0x588AD4
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#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_13 0x588AD8
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#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_14 0x588ADC
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#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_15 0x588AE0
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#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_16 0x588AE4
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#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_17 0x588AE8
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#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_18 0x588AEC
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#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_19 0x588AF0
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#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_20 0x588AF4
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#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_21 0x588AF8
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#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_22 0x588AFC
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#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_23 0x588B00
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#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_24 0x588B04
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#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_25 0x588B08
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#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_26 0x588B0C
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#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_27 0x588B10
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#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_28 0x588B14
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#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_29 0x588B18
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#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_30 0x588B1C
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#define mmDMA4_QM_ARB_MST_CHOISE_PUSH_OFST_31 0x588B20
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#define mmDMA4_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x588B28
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#define mmDMA4_QM_ARB_MST_SLAVE_EN 0x588B2C
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#define mmDMA4_QM_ARB_MST_QUIET_PER 0x588B34
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#define mmDMA4_QM_ARB_SLV_CHOISE_WDT 0x588B38
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#define mmDMA4_QM_ARB_SLV_ID 0x588B3C
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#define mmDMA4_QM_ARB_MSG_MAX_INFLIGHT 0x588B44
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#define mmDMA4_QM_ARB_MSG_AWUSER_31_11 0x588B48
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#define mmDMA4_QM_ARB_MSG_AWUSER_SEC_PROP 0x588B4C
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#define mmDMA4_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0x588B50
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#define mmDMA4_QM_ARB_BASE_LO 0x588B54
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#define mmDMA4_QM_ARB_BASE_HI 0x588B58
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#define mmDMA4_QM_ARB_STATE_STS 0x588B80
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#define mmDMA4_QM_ARB_CHOISE_FULLNESS_STS 0x588B84
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#define mmDMA4_QM_ARB_MSG_STS 0x588B88
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#define mmDMA4_QM_ARB_SLV_CHOISE_Q_HEAD 0x588B8C
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#define mmDMA4_QM_ARB_ERR_CAUSE 0x588B9C
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#define mmDMA4_QM_ARB_ERR_MSG_EN 0x588BA0
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#define mmDMA4_QM_ARB_ERR_STS_DRP 0x588BA8
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#define mmDMA4_QM_ARB_MST_CRED_STS_0 0x588BB0
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#define mmDMA4_QM_ARB_MST_CRED_STS_1 0x588BB4
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#define mmDMA4_QM_ARB_MST_CRED_STS_2 0x588BB8
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#define mmDMA4_QM_ARB_MST_CRED_STS_3 0x588BBC
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#define mmDMA4_QM_ARB_MST_CRED_STS_4 0x588BC0
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#define mmDMA4_QM_ARB_MST_CRED_STS_5 0x588BC4
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#define mmDMA4_QM_ARB_MST_CRED_STS_6 0x588BC8
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#define mmDMA4_QM_ARB_MST_CRED_STS_7 0x588BCC
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#define mmDMA4_QM_ARB_MST_CRED_STS_8 0x588BD0
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#define mmDMA4_QM_ARB_MST_CRED_STS_9 0x588BD4
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#define mmDMA4_QM_ARB_MST_CRED_STS_10 0x588BD8
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#define mmDMA4_QM_ARB_MST_CRED_STS_11 0x588BDC
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#define mmDMA4_QM_ARB_MST_CRED_STS_12 0x588BE0
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#define mmDMA4_QM_ARB_MST_CRED_STS_13 0x588BE4
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#define mmDMA4_QM_ARB_MST_CRED_STS_14 0x588BE8
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#define mmDMA4_QM_ARB_MST_CRED_STS_15 0x588BEC
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#define mmDMA4_QM_ARB_MST_CRED_STS_16 0x588BF0
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#define mmDMA4_QM_ARB_MST_CRED_STS_17 0x588BF4
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#define mmDMA4_QM_ARB_MST_CRED_STS_18 0x588BF8
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#define mmDMA4_QM_ARB_MST_CRED_STS_19 0x588BFC
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#define mmDMA4_QM_ARB_MST_CRED_STS_20 0x588C00
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#define mmDMA4_QM_ARB_MST_CRED_STS_21 0x588C04
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#define mmDMA4_QM_ARB_MST_CRED_STS_22 0x588C08
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#define mmDMA4_QM_ARB_MST_CRED_STS_23 0x588C0C
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#define mmDMA4_QM_ARB_MST_CRED_STS_24 0x588C10
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#define mmDMA4_QM_ARB_MST_CRED_STS_25 0x588C14
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#define mmDMA4_QM_ARB_MST_CRED_STS_26 0x588C18
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#define mmDMA4_QM_ARB_MST_CRED_STS_27 0x588C1C
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#define mmDMA4_QM_ARB_MST_CRED_STS_28 0x588C20
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#define mmDMA4_QM_ARB_MST_CRED_STS_29 0x588C24
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#define mmDMA4_QM_ARB_MST_CRED_STS_30 0x588C28
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#define mmDMA4_QM_ARB_MST_CRED_STS_31 0x588C2C
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#define mmDMA4_QM_CGM_CFG 0x588C70
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#define mmDMA4_QM_CGM_STS 0x588C74
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#define mmDMA4_QM_CGM_CFG1 0x588C78
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#define mmDMA4_QM_LOCAL_RANGE_BASE 0x588C80
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#define mmDMA4_QM_LOCAL_RANGE_SIZE 0x588C84
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#define mmDMA4_QM_CSMR_STRICT_PRIO_CFG 0x588C90
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#define mmDMA4_QM_HBW_RD_RATE_LIM_CFG_1 0x588C94
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#define mmDMA4_QM_LBW_WR_RATE_LIM_CFG_0 0x588C98
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#define mmDMA4_QM_LBW_WR_RATE_LIM_CFG_1 0x588C9C
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#define mmDMA4_QM_HBW_RD_RATE_LIM_CFG_0 0x588CA0
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#define mmDMA4_QM_GLBL_AXCACHE 0x588CA4
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#define mmDMA4_QM_IND_GW_APB_CFG 0x588CB0
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#define mmDMA4_QM_IND_GW_APB_WDATA 0x588CB4
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#define mmDMA4_QM_IND_GW_APB_RDATA 0x588CB8
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#define mmDMA4_QM_IND_GW_APB_STATUS 0x588CBC
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#define mmDMA4_QM_GLBL_ERR_ADDR_LO 0x588CD0
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#define mmDMA4_QM_GLBL_ERR_ADDR_HI 0x588CD4
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#define mmDMA4_QM_GLBL_ERR_WDATA 0x588CD8
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#define mmDMA4_QM_GLBL_MEM_INIT_BUSY 0x588D00
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#endif /* ASIC_REG_DMA4_QM_REGS_H_ */
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