// SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
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/*
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*
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* (C) COPYRIGHT 2022 ARM Limited. All rights reserved.
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*
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* This program is free software and is provided to you under the terms of the
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* GNU General Public License version 2 as published by the Free Software
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* Foundation, and any use by you of this program is subject to the terms
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* of such GNU license.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you can access it online at
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* http://www.gnu.org/licenses/gpl-2.0.html.
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*
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*/
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#include <linux/of_platform.h>
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#include <coresight-priv.h>
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#include "sources/coresight_mali_sources.h"
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/* Linux Coresight framework does not support multiple sources enabled
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* at the same time.
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*
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* To avoid Kernel instability, all Mali Coresight sources use the
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* same trace ID value as the mandatory ETM one.
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*/
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#define CS_MALI_TRACE_ID 0x00000010
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#define CS_SCS_BASE_ADDR 0xE000E000
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#define SCS_DEMCR 0xDFC
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#define CS_ITM_BASE_ADDR 0xE0000000
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#define ITM_TCR 0xE80
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#define ITM_TCR_BUSY_BIT (0x1 << 22)
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#define CS_DWT_BASE_ADDR 0xE0001000
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#define DWT_CTRL 0x000
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#define DWT_CYCCNT 0x004
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#if KERNEL_VERSION(5, 3, 0) <= LINUX_VERSION_CODE
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static char *type_name = "mali-source-itm";
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#endif
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#define NELEMS(s) (sizeof(s) / sizeof((s)[0]))
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enum cs_itm_dwt_dynamic_regs { CS_DWT_CTRL, CS_ITM_TCR, CS_ITM_DWT_NR_DYN_REGS };
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struct cs_itm_state {
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int enabled;
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u32 regs[CS_ITM_DWT_NR_DYN_REGS];
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};
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static struct cs_itm_state itm_state = { 0 };
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static struct kbase_debug_coresight_csf_address_range dwt_itm_range[] = {
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{ CS_SCS_BASE_ADDR, CS_SCS_BASE_ADDR + CORESIGHT_DEVTYPE },
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{ CS_ITM_BASE_ADDR, CS_ITM_BASE_ADDR + CORESIGHT_DEVTYPE },
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{ CS_DWT_BASE_ADDR, CS_DWT_BASE_ADDR + CORESIGHT_DEVTYPE }
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};
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static struct kbase_debug_coresight_csf_op dwt_itm_enable_ops[] = {
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// enable ITM/DWT functionality via DEMCR register
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WRITE_IMM_OP(CS_SCS_BASE_ADDR + SCS_DEMCR, 0x01000000),
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// Unlock DWT configuration
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WRITE_IMM_OP(CS_DWT_BASE_ADDR + CORESIGHT_LAR, CS_MALI_UNLOCK_COMPONENT),
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// prep DWT counter to immediately send sync packet ((1 << 24) - 1)
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WRITE_IMM_OP(CS_DWT_BASE_ADDR + DWT_CYCCNT, 0x00ffffff),
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// Write initial value of post count counter
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WRITE_IMM_OP(CS_DWT_BASE_ADDR + DWT_CTRL, 0x00000020),
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// Set DWT configuration:
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WRITE_PTR_OP(CS_DWT_BASE_ADDR + DWT_CTRL, &itm_state.regs[CS_DWT_CTRL]),
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// Lock DWT Configuration
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WRITE_IMM_OP(CS_DWT_BASE_ADDR + CORESIGHT_LAR, 0x00000000),
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// Unlock DWT configuration
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WRITE_IMM_OP(CS_ITM_BASE_ADDR + CORESIGHT_LAR, CS_MALI_UNLOCK_COMPONENT),
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// Set ITM configuration:
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WRITE_PTR_OP(CS_ITM_BASE_ADDR + ITM_TCR, &itm_state.regs[CS_ITM_TCR]),
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// Lock DWT configuration
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WRITE_IMM_OP(CS_ITM_BASE_ADDR + CORESIGHT_LAR, 0x00000000),
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// Set enabled bit on at the end of sequence
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BIT_OR_OP(&itm_state.enabled, 0x1),
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};
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static struct kbase_debug_coresight_csf_op dwt_itm_disable_ops[] = {
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// Disable ITM/DWT functionality via DEMCR register
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WRITE_IMM_OP(CS_SCS_BASE_ADDR + SCS_DEMCR, 0x00000000),
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// Unlock ITM configuration
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WRITE_IMM_OP(CS_ITM_BASE_ADDR + CORESIGHT_LAR, CS_MALI_UNLOCK_COMPONENT),
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// Check ITM is disabled
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POLL_OP(CS_ITM_BASE_ADDR + ITM_TCR, ITM_TCR_BUSY_BIT, 0x0),
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// Lock
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WRITE_IMM_OP(CS_ITM_BASE_ADDR + CORESIGHT_LAR, 0x00000000),
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// Set enabled bit off at the end of sequence
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BIT_AND_OP(&itm_state.enabled, 0x0),
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};
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static void set_default_regs(void)
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{
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// DWT configuration:
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// [0] = 1, enable cycle counter
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// [4:1] = 4, set PC sample rate pf 256 cycles
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// [8:5] = 1, set initial post count value
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// [9] = 1, select position of post count tap on the cycle counter
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// [10:11] = 1, enable sync packets
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// [12] = 1, enable periodic PC sample packets
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itm_state.regs[CS_DWT_CTRL] = 0x00001629;
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// ITM configuration:
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// [0] = 1, Enable ITM
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// [1] = 1, Enable Time stamp generation
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// [2] = 1, Enable sync packet transmission
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// [3] = 1, Enable HW event forwarding
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// [11:10] = 1, Generate TS request approx every 128 cycles
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// [22:16] = 1, Trace bus ID
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itm_state.regs[CS_ITM_TCR] = 0x0001040F;
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}
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static int verify_store_reg(struct device *dev, const char *buf, size_t count, int reg)
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{
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struct coresight_mali_source_drvdata *drvdata = dev_get_drvdata(dev->parent);
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u32 val;
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int err;
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if (buf == NULL)
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return -EINVAL;
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if (itm_state.enabled == 1) {
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dev_err(drvdata->base.dev,
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"Config needs to be disabled before modifying registers\n");
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return -EINVAL;
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}
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err = kstrtou32(buf, 0, &val);
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if (err) {
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dev_err(drvdata->base.dev, "Invalid input value\n");
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return -EINVAL;
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}
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itm_state.regs[reg] = val;
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return count;
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}
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static ssize_t is_enabled_show(struct device *dev, struct device_attribute *attr, char *const buf)
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{
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return sprintf(buf, "%d\n", itm_state.enabled);
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}
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static DEVICE_ATTR_RO(is_enabled);
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#define CS_ITM_DWT_REG_ATTR_RW(_a, _b) \
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static ssize_t _a##_show(struct device *dev, struct device_attribute *attr, \
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char *const buf) \
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{ \
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return sprintf(buf, "%#x\n", itm_state.regs[CS_##_b]); \
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} \
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static ssize_t _a##_store(struct device *dev, struct device_attribute *attr, \
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const char *buf, size_t count) \
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{ \
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return verify_store_reg(dev, buf, count, CS_##_b); \
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} \
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static DEVICE_ATTR_RW(_a)
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CS_ITM_DWT_REG_ATTR_RW(dwt_ctrl, DWT_CTRL);
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CS_ITM_DWT_REG_ATTR_RW(itm_tcr, ITM_TCR);
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static struct attribute *coresight_mali_source_attrs[] = {
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&dev_attr_is_enabled.attr,
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&dev_attr_dwt_ctrl.attr,
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&dev_attr_itm_tcr.attr,
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NULL,
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};
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static const struct attribute_group coresight_mali_source_group = {
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.attrs = coresight_mali_source_attrs,
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.name = "mgmt"
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};
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static const struct attribute_group *coresight_mali_source_groups[] = {
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&coresight_mali_source_group,
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NULL,
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};
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const struct attribute_group **coresight_mali_source_groups_get(void)
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{
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return coresight_mali_source_groups;
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}
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int coresight_mali_sources_init_drvdata(struct coresight_mali_source_drvdata *drvdata)
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{
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if (drvdata == NULL)
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return -EINVAL;
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#if KERNEL_VERSION(5, 3, 0) <= LINUX_VERSION_CODE
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drvdata->type_name = type_name;
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#endif
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drvdata->base.kbase_client = kbase_debug_coresight_csf_register(
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drvdata->base.gpu_dev, dwt_itm_range, NELEMS(dwt_itm_range));
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if (drvdata->base.kbase_client == NULL) {
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dev_err(drvdata->base.dev, "Registration with full range failed unexpectedly\n");
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return -EINVAL;
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}
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drvdata->trcid = CS_MALI_TRACE_ID;
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drvdata->base.enable_seq.ops = dwt_itm_enable_ops;
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drvdata->base.enable_seq.nr_ops = NELEMS(dwt_itm_enable_ops);
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drvdata->base.disable_seq.ops = dwt_itm_disable_ops;
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drvdata->base.disable_seq.nr_ops = NELEMS(dwt_itm_disable_ops);
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set_default_regs();
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drvdata->base.config = kbase_debug_coresight_csf_config_create(
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drvdata->base.kbase_client, &drvdata->base.enable_seq, &drvdata->base.disable_seq);
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if (!drvdata->base.config) {
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dev_err(drvdata->base.dev, "config create failed unexpectedly\n");
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kbase_debug_coresight_csf_unregister(drvdata->base.kbase_client);
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return -EINVAL;
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}
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return 0;
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}
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void coresight_mali_sources_deinit_drvdata(struct coresight_mali_source_drvdata *drvdata)
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{
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if (drvdata->base.config != NULL)
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kbase_debug_coresight_csf_config_free(drvdata->base.config);
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if (drvdata->base.kbase_client != NULL)
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kbase_debug_coresight_csf_unregister(drvdata->base.kbase_client);
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}
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static const struct of_device_id mali_source_ids[] = { { .compatible =
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"arm,coresight-mali-source-itm" },
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{} };
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static struct platform_driver mali_sources_platform_driver = {
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.probe = coresight_mali_sources_probe,
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.remove = coresight_mali_sources_remove,
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.driver = {
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.name = "coresight-mali-source-itm",
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.owner = THIS_MODULE,
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.of_match_table = mali_source_ids,
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.suppress_bind_attrs = true,
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},
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};
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static int __init mali_sources_init(void)
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{
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return platform_driver_register(&mali_sources_platform_driver);
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}
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static void __exit mali_sources_exit(void)
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{
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platform_driver_unregister(&mali_sources_platform_driver);
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}
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module_init(mali_sources_init);
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module_exit(mali_sources_exit);
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MODULE_AUTHOR("ARM Ltd.");
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MODULE_DESCRIPTION("Arm Coresight Mali source ITM");
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MODULE_LICENSE("GPL");
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