// SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
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/*
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*
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* (C) COPYRIGHT 2022 ARM Limited. All rights reserved.
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*
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* This program is free software and is provided to you under the terms of the
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* GNU General Public License version 2 as published by the Free Software
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* Foundation, and any use by you of this program is subject to the terms
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* of such GNU license.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you can access it online at
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* http://www.gnu.org/licenses/gpl-2.0.html.
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*
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*/
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#include <linux/of_platform.h>
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#include <coresight-priv.h>
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#include <coresight-etm4x.h>
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#include "sources/coresight_mali_sources.h"
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#define CS_ETM_BASE_ADDR 0xE0041000
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#define CS_MALI_TRACE_ID 0x00000010
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#ifndef TRCVICTLR_SSSTATUS
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#define TRCVICTLR_SSSTATUS BIT(9)
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#endif
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#if KERNEL_VERSION(5, 3, 0) <= LINUX_VERSION_CODE
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static char *type_name = "mali-source-etm";
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#endif
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#define NELEMS(s) (sizeof(s) / sizeof((s)[0]))
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enum cs_etm_dynamic_regs {
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CS_ETM_TRCCONFIGR,
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CS_ETM_TRCTRACEIDR,
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CS_ETM_TRCVDARCCTLR,
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CS_ETM_TRCSTALLCTLR,
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CS_ETM_TRCVIIECTLR,
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CS_ETM_NR_DYN_REGS
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};
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struct cs_etm_state {
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int enabled;
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u32 regs[CS_ETM_NR_DYN_REGS];
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};
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static struct cs_etm_state etm_state = { 0 };
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static struct kbase_debug_coresight_csf_address_range etm_range[] = {
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{ CS_ETM_BASE_ADDR, CS_ETM_BASE_ADDR + CORESIGHT_DEVTYPE },
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};
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struct kbase_debug_coresight_csf_op etm_enable_ops[] = {
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// Unlock ETM configuration
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WRITE_IMM_OP(CS_ETM_BASE_ADDR + CORESIGHT_LAR, CS_MALI_UNLOCK_COMPONENT),
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// Power up request
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WRITE_IMM_OP(CS_ETM_BASE_ADDR + TRCPDCR, TRCPDCR_PU),
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// Disable Tracing
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WRITE_IMM_OP(CS_ETM_BASE_ADDR + TRCPRGCTLR, 0x00000000),
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// Check the tracing unit is inactive before programming
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POLL_OP(CS_ETM_BASE_ADDR + TRCSTATR, BIT(TRCSTATR_IDLE_BIT), BIT(TRCSTATR_IDLE_BIT)),
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// Set trace configuration to enable global timestamping, and data value tracing
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WRITE_PTR_OP(CS_ETM_BASE_ADDR + TRCCONFIGR, &etm_state.regs[CS_ETM_TRCCONFIGR]),
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// Set event control 0 register
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WRITE_IMM_OP(CS_ETM_BASE_ADDR + TRCEVENTCTL0R, 0x00000000),
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// Set event control 1 register
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WRITE_IMM_OP(CS_ETM_BASE_ADDR + TRCEVENTCTL1R, 0x00000000),
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// Set trace ID
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WRITE_PTR_OP(CS_ETM_BASE_ADDR + TRCTRACEIDR, &etm_state.regs[CS_ETM_TRCTRACEIDR]),
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// Configure stall control register
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WRITE_PTR_OP(CS_ETM_BASE_ADDR + TRCSTALLCTLR, &etm_state.regs[CS_ETM_TRCSTALLCTLR]),
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// Synchronization period register - sync every 2^11 bytes
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WRITE_IMM_OP(CS_ETM_BASE_ADDR + TRCSYNCPR, 0x0000000C),
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// Set global timestamp control register to select resource 0
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WRITE_IMM_OP(CS_ETM_BASE_ADDR + TRCTSCTLR, 0x00000000),
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// Set viewData include/exclude address range comparators to 0
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WRITE_PTR_OP(CS_ETM_BASE_ADDR + TRCVDARCCTLR, &etm_state.regs[CS_ETM_TRCVDARCCTLR]),
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// Set viewData main control to select resource 0
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WRITE_IMM_OP(CS_ETM_BASE_ADDR + TRCVDCTLR, 0x00000001),
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//Set viewData comparators to 0
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WRITE_IMM_OP(CS_ETM_BASE_ADDR + TRCVDSACCTLR, 0x00000000),
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// Set stop/start logic to started state, select resource 1
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WRITE_IMM_OP(CS_ETM_BASE_ADDR + TRCVICTLR, TRCVICTLR_SSSTATUS | BIT(0)),
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// Set viewInst start and stop control
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WRITE_IMM_OP(CS_ETM_BASE_ADDR + TRCVISSCTLR, 0x00000000),
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// Set viewInst include and exclude control to math all addresses in range
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WRITE_PTR_OP(CS_ETM_BASE_ADDR + TRCVIIECTLR, &etm_state.regs[CS_ETM_TRCVIIECTLR]),
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// enable trace
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WRITE_IMM_OP(CS_ETM_BASE_ADDR + TRCPRGCTLR, 0x1),
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// Wait that the unit is busy
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POLL_OP(CS_ETM_BASE_ADDR + TRCSTATR, BIT(TRCSTATR_IDLE_BIT), 0),
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// Lock the ETM configuration
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WRITE_IMM_OP(CS_ETM_BASE_ADDR + CORESIGHT_LAR, 0x00000000),
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// Set enabled bit on at the end of sequence
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BIT_OR_OP(&etm_state.enabled, 0x1),
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};
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struct kbase_debug_coresight_csf_op etm_disable_ops[] = {
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// Unlock ETM configuration
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WRITE_IMM_OP(CS_ETM_BASE_ADDR + CORESIGHT_LAR, CS_MALI_UNLOCK_COMPONENT),
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// Disable trace unit
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WRITE_IMM_OP(CS_ETM_BASE_ADDR + TRCPRGCTLR, 0x00000000),
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// Poll until idle
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POLL_OP(CS_ETM_BASE_ADDR + TRCSTATR, BIT(TRCSTATR_IDLE_BIT), BIT(TRCSTATR_IDLE_BIT)),
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// Lock ETM configuration
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WRITE_IMM_OP(CS_ETM_BASE_ADDR + CORESIGHT_LAR, 0x00000000),
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// Set enabled bit off at the end of sequence
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BIT_AND_OP(&etm_state.enabled, 0x0),
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};
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static void set_default_regs(void)
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{
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// Turn on instruction tracing
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etm_state.regs[CS_ETM_TRCCONFIGR] = 0x00000800;
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// Set ID
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etm_state.regs[CS_ETM_TRCTRACEIDR] = CS_MALI_TRACE_ID;
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// Set data comparators to none
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etm_state.regs[CS_ETM_TRCVDARCCTLR] = 0x00000000;
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// Set instructions address filter to none
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etm_state.regs[CS_ETM_TRCVIIECTLR] = 0x00000000;
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// Set stall configuration to a basic setting
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etm_state.regs[CS_ETM_TRCSTALLCTLR] = 0x00000000;
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}
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static const struct of_device_id mali_source_ids[] = { { .compatible =
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"arm,coresight-mali-source-etm" },
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{} };
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int coresight_mali_sources_init_drvdata(struct coresight_mali_source_drvdata *drvdata)
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{
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int ret = 0;
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if (drvdata == NULL)
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return -EINVAL;
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#if KERNEL_VERSION(5, 3, 0) <= LINUX_VERSION_CODE
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drvdata->type_name = type_name;
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#endif
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etm_state.enabled = 0x0;
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drvdata->base.kbase_client = kbase_debug_coresight_csf_register(
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drvdata->base.gpu_dev, etm_range, NELEMS(etm_range));
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if (drvdata->base.kbase_client == NULL) {
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dev_err(drvdata->base.dev, "Registration with full range failed unexpectedly\n");
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return -EINVAL;
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}
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set_default_regs();
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drvdata->trcid = CS_MALI_TRACE_ID;
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drvdata->base.enable_seq.ops = etm_enable_ops;
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drvdata->base.enable_seq.nr_ops = NELEMS(etm_enable_ops);
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drvdata->base.disable_seq.ops = etm_disable_ops;
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drvdata->base.disable_seq.nr_ops = NELEMS(etm_disable_ops);
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drvdata->base.config = kbase_debug_coresight_csf_config_create(
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drvdata->base.kbase_client, &drvdata->base.enable_seq, &drvdata->base.disable_seq);
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if (!drvdata->base.config) {
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dev_err(drvdata->base.dev, "Config create failed unexpectedly\n");
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kbase_debug_coresight_csf_unregister(drvdata->base.kbase_client);
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return -EINVAL;
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}
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return ret;
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}
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void coresight_mali_sources_deinit_drvdata(struct coresight_mali_source_drvdata *drvdata)
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{
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if (drvdata->base.config != NULL)
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kbase_debug_coresight_csf_config_free(drvdata->base.config);
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if (drvdata->base.kbase_client != NULL)
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kbase_debug_coresight_csf_unregister(drvdata->base.kbase_client);
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}
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static int verify_store_reg(struct device *dev, const char *buf, size_t count, int reg)
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{
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struct coresight_mali_source_drvdata *drvdata = dev_get_drvdata(dev->parent);
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u32 val;
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int err;
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if (buf == NULL)
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return -EINVAL;
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if (etm_state.enabled == 1) {
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dev_err(drvdata->base.dev,
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"Config needs to be disabled before modifying registers\n");
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return -EINVAL;
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}
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err = kstrtou32(buf, 0, &val);
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if (err) {
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dev_err(drvdata->base.dev, "Invalid input value\n");
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return -EINVAL;
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}
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etm_state.regs[reg] = val;
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return count;
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}
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#define CS_ETM_REG_ATTR_RW(_a, _b) \
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static ssize_t _a##_show(struct device *dev, struct device_attribute *attr, \
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char *const buf) \
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{ \
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return sprintf(buf, "%#x\n", etm_state.regs[CS_ETM_##_b]); \
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} \
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static ssize_t _a##_store(struct device *dev, struct device_attribute *attr, \
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const char *buf, size_t count) \
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{ \
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return verify_store_reg(dev, buf, count, CS_ETM_##_b); \
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} \
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static DEVICE_ATTR_RW(_a)
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CS_ETM_REG_ATTR_RW(trcconfigr, TRCCONFIGR);
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CS_ETM_REG_ATTR_RW(trctraceidr, TRCTRACEIDR);
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CS_ETM_REG_ATTR_RW(trcvdarcctlr, TRCVDARCCTLR);
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CS_ETM_REG_ATTR_RW(trcviiectlr, TRCVIIECTLR);
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CS_ETM_REG_ATTR_RW(trcstallctlr, TRCSTALLCTLR);
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static ssize_t is_enabled_show(struct device *dev, struct device_attribute *attr, char *const buf)
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{
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return sprintf(buf, "%d\n", etm_state.enabled);
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}
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static DEVICE_ATTR_RO(is_enabled);
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static struct attribute *coresight_etm_attrs[] = {
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&dev_attr_is_enabled.attr,
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&dev_attr_trcconfigr.attr,
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&dev_attr_trctraceidr.attr,
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&dev_attr_trcvdarcctlr.attr,
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&dev_attr_trcviiectlr.attr,
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&dev_attr_trcstallctlr.attr,
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NULL,
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};
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static struct attribute_group coresight_etm_group = { .attrs = coresight_etm_attrs,
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.name = "mgmt" };
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static const struct attribute_group *coresight_etm_groups[] = {
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&coresight_etm_group,
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NULL,
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};
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const struct attribute_group **coresight_mali_source_groups_get(void)
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{
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return coresight_etm_groups;
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}
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static struct platform_driver mali_sources_platform_driver = {
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.probe = coresight_mali_sources_probe,
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.remove = coresight_mali_sources_remove,
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.driver = {
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.name = "coresight-mali-source-etm",
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.owner = THIS_MODULE,
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.of_match_table = mali_source_ids,
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.suppress_bind_attrs = true,
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},
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};
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static int __init mali_sources_init(void)
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{
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return platform_driver_register(&mali_sources_platform_driver);
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}
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static void __exit mali_sources_exit(void)
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{
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platform_driver_unregister(&mali_sources_platform_driver);
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}
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module_init(mali_sources_init);
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module_exit(mali_sources_exit);
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MODULE_AUTHOR("ARM Ltd.");
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MODULE_DESCRIPTION("Arm Coresight Mali source ETM");
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MODULE_LICENSE("GPL");
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