/*
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* Copyright 2016 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "gk104.h"
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#include "changk104.h"
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#include <core/gpuobj.h>
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#include <subdev/fault.h>
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#include <nvif/class.h>
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static void
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gm107_fifo_runlist_chan(struct gk104_fifo_chan *chan,
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struct nvkm_memory *memory, u32 offset)
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{
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nvkm_wo32(memory, offset + 0, chan->base.chid);
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nvkm_wo32(memory, offset + 4, chan->base.inst->addr >> 12);
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}
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const struct gk104_fifo_runlist_func
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gm107_fifo_runlist = {
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.size = 8,
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.cgrp = gk110_fifo_runlist_cgrp,
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.chan = gm107_fifo_runlist_chan,
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.commit = gk104_fifo_runlist_commit,
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};
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const struct nvkm_enum
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gm107_fifo_fault_engine[] = {
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{ 0x01, "DISPLAY" },
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{ 0x02, "CAPTURE" },
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{ 0x03, "IFB", NULL, NVKM_ENGINE_IFB },
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{ 0x04, "BAR1", NULL, NVKM_SUBDEV_BAR },
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{ 0x05, "BAR2", NULL, NVKM_SUBDEV_INSTMEM },
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{ 0x06, "SCHED" },
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{ 0x07, "HOST0", NULL, NVKM_ENGINE_FIFO },
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{ 0x08, "HOST1", NULL, NVKM_ENGINE_FIFO },
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{ 0x09, "HOST2", NULL, NVKM_ENGINE_FIFO },
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{ 0x0a, "HOST3", NULL, NVKM_ENGINE_FIFO },
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{ 0x0b, "HOST4", NULL, NVKM_ENGINE_FIFO },
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{ 0x0c, "HOST5", NULL, NVKM_ENGINE_FIFO },
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{ 0x0d, "HOST6", NULL, NVKM_ENGINE_FIFO },
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{ 0x0e, "HOST7", NULL, NVKM_ENGINE_FIFO },
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{ 0x0f, "HOSTSR" },
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{ 0x13, "PERF" },
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{ 0x17, "PMU" },
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{ 0x18, "PTP" },
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{}
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};
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void
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gm107_fifo_intr_fault(struct nvkm_fifo *fifo, int unit)
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{
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struct nvkm_device *device = fifo->engine.subdev.device;
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u32 inst = nvkm_rd32(device, 0x002800 + (unit * 0x10));
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u32 valo = nvkm_rd32(device, 0x002804 + (unit * 0x10));
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u32 vahi = nvkm_rd32(device, 0x002808 + (unit * 0x10));
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u32 type = nvkm_rd32(device, 0x00280c + (unit * 0x10));
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struct nvkm_fault_data info;
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info.inst = (u64)inst << 12;
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info.addr = ((u64)vahi << 32) | valo;
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info.time = 0;
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info.engine = unit;
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info.valid = 1;
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info.gpc = (type & 0x1f000000) >> 24;
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info.client = (type & 0x00003f00) >> 8;
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info.access = (type & 0x00000080) >> 7;
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info.hub = (type & 0x00000040) >> 6;
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info.reason = (type & 0x0000000f);
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nvkm_fifo_fault(fifo, &info);
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}
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static const struct gk104_fifo_func
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gm107_fifo = {
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.intr.fault = gm107_fifo_intr_fault,
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.pbdma = &gk208_fifo_pbdma,
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.fault.access = gk104_fifo_fault_access,
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.fault.engine = gm107_fifo_fault_engine,
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.fault.reason = gk104_fifo_fault_reason,
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.fault.hubclient = gk104_fifo_fault_hubclient,
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.fault.gpcclient = gk104_fifo_fault_gpcclient,
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.runlist = &gm107_fifo_runlist,
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.chan = {{0,0,KEPLER_CHANNEL_GPFIFO_B}, gk104_fifo_gpfifo_new },
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};
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int
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gm107_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo)
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{
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return gk104_fifo_new_(&gm107_fifo, device, index, 2048, pfifo);
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}
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