/** @file
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Copyright (c) 2011 - 2019, Intel Corporaton. All rights reserved.
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SPDX-License-Identifier: BSD-2-Clause-Patent
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The original software modules are licensed as follows:
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Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
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Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef EMAC_DXE_UTIL_H__
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#define EMAC_DXE_UTIL_H__
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#include <Protocol/SimpleNetwork.h>
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// Most common CRC32 Polynomial for little endian machines
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#define CRC_POLYNOMIAL 0xEDB88320
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#define HASH_TABLE_REG(n) 0x500 + (0x4 * n)
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#define RX_MAX_PACKET 1600
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#define CONFIG_ETH_BUFSIZE 2048
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#define CONFIG_TX_DESCR_NUM 10
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#define CONFIG_RX_DESCR_NUM 10
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#define TX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM)
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#define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM)
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// DMA status error bit
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#define RX_DMA_WRITE_DATA_TRANSFER_ERROR 0x0
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#define TX_DMA_READ_DATA_TRANSFER_ERROR 0x3
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#define RX_DMA_DESCRIPTOR_WRITE_ACCESS_ERROR 0x4
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#define TX_DMA_DESCRIPTOR_WRITE_ACCESS_ERROR 0x5
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#define RX_DMA_DESCRIPTOR_READ_ACCESS_ERROR 0x6
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#define TX_DMA_DESCRIPTOR_READ_ACCESS_ERROR 0x7
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// tx descriptor
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#define TDES0_OWN BIT31
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#define TDES0_TXINT BIT30
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#define TDES0_TXLAST BIT29
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#define TDES0_TXFIRST BIT28
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#define TDES0_TXCRCDIS BIT27
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#define TDES0_TXRINGEND BIT21
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#define TDES0_TXCHAIN BIT20
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#define TDES1_SIZE1MASK (0x1FFF << 0)
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#define TDES1_SIZE1SHFT (0)
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#define TDES1_SIZE2MASK (0x1FFF << 16)
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#define TDES1_SIZE2SHFT (16)
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// rx descriptor
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#define RDES0_FL_MASK 0x3fff
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#define RDES0_FL_SHIFT 16
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#define RDES1_CHAINED BIT14
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#define RDES0_CE BIT1
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#define RDES0_DBE BIT2
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#define RDES0_RE BIT3
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#define RDES0_RWT BIT4
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#define RDES0_LC BIT6
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#define RDES0_GF BIT7
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#define RDES0_OE BIT11
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#define RDES0_LE BIT12
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#define RDES0_SAF BIT13
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#define RDES0_DE BIT14
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#define RDES0_ES BIT15
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#define RDES0_AFM BIT30
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#define RDES0_OWN BIT31
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// emac config phy interface setting
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#define PHY_INTERFACE_MODE_GMII 0
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#define PHY_INTERFACE_MODE_MII 1
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#define PHY_INTERFACE_MODE_RGMII 2
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#define PHY_INTERFACE_MODE_RMII 3
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// DW emac mask
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#define DW_EMAC_DMAGRP_BUS_MODE_SWR_SET_MSK 0x00000001
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#define DW_EMAC_DMAGRP_BUS_MODE_FB_SET_MSK 0x00010000
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#define DW_EMAC_DMAGRP_BUS_MODE_PBL_SET_MSK 0x00003f00
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#define DW_EMAC_DMAGRP_BUS_MODE_PR_SET_MSK 0x0000c000
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#define DW_EMAC_DMAGRP_OPERATION_MODE_FTF_SET_MSK 0x00100000
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#define DW_EMAC_DMAGRP_OPERATION_MODE_TSF_SET_MSK 0x00200000
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#define DW_EMAC_DMAGRP_INTERRUPT_ENABLE_TIE_SET_MSK 0x00000001
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#define DW_EMAC_DMAGRP_INTERRUPT_ENABLE_RIE_SET_MSK 0x00000040
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#define DW_EMAC_DMAGRP_INTERRUPT_ENABLE_NIE_SET_MSK 0x00010000
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#define DW_EMAC_DMAGRP_INTERRUPT_ENABLE_AIE_SET_MSK 0x00008000
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#define DW_EMAC_DMAGRP_INTERRUPT_ENABLE_FBE_SET_MSK 0x00002000
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#define DW_EMAC_DMAGRP_INTERRUPT_ENABLE_UNE_SET_MSK 0x00000020
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#define DW_EMAC_DMAGRP_INTERRUPT_ENABLE_TSE_SET_MSK 0x00000002
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#define DW_EMAC_DMAGRP_INTERRUPT_ENABLE_TUE_SET_MSK 0x00000004
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#define DW_EMAC_DMAGRP_INTERRUPT_ENABLE_TJE_SET_MSK 0x00000008
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#define DW_EMAC_DMAGRP_INTERRUPT_ENABLE_OVE_SET_MSK 0x00000010
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#define DW_EMAC_DMAGRP_INTERRUPT_ENABLE_RUE_SET_MSK 0x00000080
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#define DW_EMAC_DMAGRP_INTERRUPT_ENABLE_RSE_SET_MSK 0x00000100
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#define DW_EMAC_DMAGRP_INTERRUPT_ENABLE_RWE_SET_MSK 0x00000200
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#define DW_EMAC_DMAGRP_INTERRUPT_ENABLE_ETE_SET_MSK 0x00000400
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#define DW_EMAC_DMAGRP_INTERRUPT_ENABLE_ERE_SET_MSK 0x00004000
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#define DW_EMAC_DMAGRP_OPERATION_MODE_ST_SET_MSK 0x00002000
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#define DW_EMAC_DMAGRP_OPERATION_MODE_SR_SET_MSK 0x00000002
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#define DW_EMAC_GMACGRP_MAC_CONFIGURATION_RE_SET_MSK 0x00000004
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#define DW_EMAC_GMACGRP_MAC_CONFIGURATION_TE_SET_MSK 0x00000008
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#define DW_EMAC_GMACGRP_MAC_FRAME_FILTER_RESET 0x00000000
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#define DW_EMAC_GMACGRP_MAC_FRAME_FILTER_HMC_SET_MSK 0x00000004
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#define DW_EMAC_GMACGRP_MAC_FRAME_FILTER_DBF_SET_MSK 0x00000020
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#define DW_EMAC_GMACGRP_MAC_FRAME_FILTER_PR_SET_MSK 0x00000001
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#define DW_EMAC_GMACGRP_MAC_FRAME_FILTER_PM_SET_MSK 0x00000010
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#define DW_EMAC_DMAGRP_OPERATION_MODE_ST_CLR_MSK 0xffffdfff
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#define DW_EMAC_GMACGRP_MAC_CONFIGURATION_RE_CLR_MSK 0xfffffffb
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#define DW_EMAC_GMACGRP_MAC_CONFIGURATION_TE_CLR_MSK 0xfffffff7
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#define DW_EMAC_DMAGRP_OPERATION_MODE_SR_CLR_MSK 0xfffffffd
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#define DW_EMAC_DMAGRP_STATUS_NIS_SET_MSK 0x00010000
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#define DW_EMAC_DMAGRP_STATUS_RI_SET_MSK 0x00000040
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#define DW_EMAC_DMAGRP_STATUS_TI_SET_MSK 0x00000001
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#define DW_EMAC_DMAGRP_STATUS_TU_SET_MSK 0x00000004
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#define DW_EMAC_DMAGRP_STATUS_ERI_SET_MSK 0x00004000
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#define DW_EMAC_DMAGRP_STATUS_AIS_SET_MSK 0x00008000
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#define DW_EMAC_DMAGRP_STATUS_TPS_SET_MSK 0x00000002
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#define DW_EMAC_DMAGRP_STATUS_TJT_SET_MSK 0x00000008
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#define DW_EMAC_DMAGRP_STATUS_OVF_SET_MSK 0x00000010
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#define DW_EMAC_DMAGRP_STATUS_UNF_SET_MSK 0x00000020
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#define DW_EMAC_DMAGRP_STATUS_RU_SET_MSK 0x00000080
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#define DW_EMAC_DMAGRP_STATUS_RPS_SET_MSK 0x00000100
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#define DW_EMAC_DMAGRP_STATUS_RWT_SET_MSK 0x00000200
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#define DW_EMAC_DMAGRP_STATUS_ETI_SET_MSK 0x00000400
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#define DW_EMAC_DMAGRP_STATUS_FBI_SET_MSK 0x00002000
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#define DW_EMAC_GMACGRP_MAC_CONFIGURATION_PS_SET_MSK 0x00008000
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#define DW_EMAC_GMACGRP_MAC_CONFIGURATION_FES_SET_MSK 0x00004000
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#define DW_EMAC_GMACGRP_MAC_CONFIGURATION_DM_SET_MSK 0x00000800
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#define DW_EMAC_GMACGRP_MAC_CONFIGURATION_BE_SET_MSK 0x00200000
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#define DW_EMAC_GMACGRP_MAC_CONFIGURATION_DO_SET_MSK 0x00002000
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#define DW_EMAC_DMAGRP_BUS_MODE_SWR_GET(value) (((value) & 0x00000001) >> 0)
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#define DW_EMAC_DMAGRP_STATUS_EB_GET(value) (((value) & 0x03800000) >> 23)
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#define DW_EMAC_GMACGRP_GMII_ADDRESS_GB_GET(value) (((value) & 0x00000001) >> 0)
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#define DW_EMAC_GMACGRP_GMII_DATA_GD_GET(value) (((value) & 0x0000ffff) >> 0)
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#define DW_EMAC_DMAGRP_OPERATION_MODE_FTF_GET(value) (((value) & 0x00100000) >> 20)
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// DW emac registers offset
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#define DW_EMAC_GMACGRP_MAC_CONFIGURATION_OFST 0x000
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#define DW_EMAC_GMACGRP_MAC_FRAME_FILTER_OFST 0x004
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#define DW_EMAC_GMACGRP_GMII_ADDRESS_OFST 0x010
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#define DW_EMAC_GMACGRP_GMII_DATA_OFST 0x014
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#define DW_EMAC_GMACGRP_FLOW_CONTROL_OFST 0x018
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#define DW_EMAC_GMACGRP_VLAN_TAG_OFST 0x01c
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#define DW_EMAC_GMACGRP_VERSION_OFST 0x020
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#define DW_EMAC_GMACGRP_DEBUG_OFST 0x024
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#define DW_EMAC_GMACGRP_LPI_CONTROL_STATUS_OFST 0x030
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#define DW_EMAC_GMACGRP_LPI_TIMERS_CONTROL_OFST 0x034
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#define DW_EMAC_GMACGRP_INTERRUPT_STATUS_OFST 0x038
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#define DW_EMAC_GMACGRP_INTERRUPT_MASK_OFST 0x03c
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#define DW_EMAC_GMACGRP_MAC_ADDRESS0_HIGH_OFST 0x040
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#define DW_EMAC_GMACGRP_MAC_ADDRESS0_LOW_OFST 0x044
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#define DW_EMAC_GMACGRP_MAC_ADDRESS1_HIGH_OFST 0x048
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#define DW_EMAC_GMACGRP_MAC_ADDRESS1_LOW_OFST 0x04c
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#define DW_EMAC_GMACGRP_MAC_ADDRESS2_HIGH_OFST 0x050
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#define DW_EMAC_GMACGRP_MAC_ADDRESS2_LOW_OFST 0x054
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#define DW_EMAC_GMACGRP_MAC_ADDRESS3_HIGH_OFST 0x058
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#define DW_EMAC_GMACGRP_MAC_ADDRESS3_LOW_OFST 0x05c
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#define DW_EMAC_GMACGRP_MAC_ADDRESS4_HIGH_OFST 0x060
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#define DW_EMAC_GMACGRP_MAC_ADDRESS4_LOW_OFST 0x064
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#define DW_EMAC_GMACGRP_MAC_ADDRESS5_HIGH_OFST 0x068
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#define DW_EMAC_GMACGRP_MAC_ADDRESS5_LOW_OFST 0x06c
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#define DW_EMAC_GMACGRP_MAC_ADDRESS6_HIGH_OFST 0x070
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#define DW_EMAC_GMACGRP_MAC_ADDRESS6_LOW_OFST 0x074
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#define DW_EMAC_GMACGRP_MAC_ADDRESS7_HIGH_OFST 0x078
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#define DW_EMAC_GMACGRP_MAC_ADDRESS7_LOW_OFST 0x07c
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#define DW_EMAC_GMACGRP_MAC_ADDRESS8_HIGH_OFST 0x080
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#define DW_EMAC_GMACGRP_MAC_ADDRESS8_LOW_OFST 0x084
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#define DW_EMAC_GMACGRP_MAC_ADDRESS9_HIGH_OFST 0x088
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#define DW_EMAC_GMACGRP_MAC_ADDRESS9_LOW_OFST 0x08c
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#define DW_EMAC_GMACGRP_MAC_ADDRESS10_HIGH_OFST 0x090
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#define DW_EMAC_GMACGRP_MAC_ADDRESS10_LOW_OFST 0x094
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#define DW_EMAC_GMACGRP_MAC_ADDRESS11_HIGH_OFST 0x098
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#define DW_EMAC_GMACGRP_MAC_ADDRESS11_LOW_OFST 0x09c
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#define DW_EMAC_GMACGRP_MAC_ADDRESS12_HIGH_OFST 0x0a0
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#define DW_EMAC_GMACGRP_MAC_ADDRESS12_LOW_OFST 0x0a4
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#define DW_EMAC_GMACGRP_MAC_ADDRESS13_HIGH_OFST 0x0a8
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#define DW_EMAC_GMACGRP_MAC_ADDRESS13_LOW_OFST 0x0ac
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#define DW_EMAC_GMACGRP_MAC_ADDRESS14_HIGH_OFST 0x0b0
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#define DW_EMAC_GMACGRP_MAC_ADDRESS14_LOW_OFST 0x0b4
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#define DW_EMAC_GMACGRP_MAC_ADDRESS15_HIGH_OFST 0x0b8
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#define DW_EMAC_GMACGRP_MAC_ADDRESS15_LOW_OFST 0x0bc
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#define DW_EMAC_GMACGRP_SGMII_RGMII_SMII_CONTROL_STATUS_OFST 0x0d8
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#define DW_EMAC_GMACGRP_WDOG_TIMEOUT_OFST 0x0dc
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#define DW_EMAC_GMACGRP_GENPIO_OFST 0x0e0
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#define DW_EMAC_GMACGRP_MMC_CONTROL_OFST 0x100
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#define DW_EMAC_GMACGRP_MMC_RECEIVE_INTERRUPT_OFST 0x104
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#define DW_EMAC_GMACGRP_MMC_TRANSMIT_INTERRUPT_OFST 0x108
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#define DW_EMAC_GMACGRP_MMC_RECEIVE_INTERRUPT_MASK_OFST 0x10c
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#define DW_EMAC_GMACGRP_MMC_TRANSMIT_INTERRUPT_MASK_OFST 0x110
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#define DW_EMAC_GMACGRP_TXOCTETCOUNT_GB_OFST 0x114
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#define DW_EMAC_GMACGRP_TXFRAMECOUNT_GB_OFST 0x118
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#define DW_EMAC_GMACGRP_TXBROADCASTFRAMES_G_OFST 0x11c
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#define DW_EMAC_GMACGRP_TXMULTICASTFRAMES_G_OFST 0x120
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#define DW_EMAC_GMACGRP_TXUNICASTFRAMES_GB_OFST 0x13c
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#define DW_EMAC_GMACGRP_TXLATECOL_OFST 0x158
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#define DW_EMAC_GMACGRP_TXEXESSCOL_OFST 0x15c
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#define DW_EMAC_GMACGRP_TXFRAMECOUNT_G_OFST 0x168
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#define DW_EMAC_GMACGRP_TXOVERSIZE_G_OFST 0x178
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#define DW_EMAC_GMACGRP_RXFRAMECOUNT_GB_OFST 0x180
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#define DW_EMAC_GMACGRP_RXOCTETCOUNT_GB_OFST 0x184
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#define DW_EMAC_GMACGRP_RXBROADCASTFRAMES_G_OFST 0x18c
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#define DW_EMAC_GMACGRP_RXMULTICASTFRAMES_G_OFST 0x190
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#define DW_EMAC_GMACGRP_RXCRCERROR_OFST 0x194
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#define DW_EMAC_GMACGRP_RXUNDERSIZE_G_OFST 0x1a4
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#define DW_EMAC_GMACGRP_RXOVERSIZE_G_OFST 0x1a8
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#define DW_EMAC_GMACGRP_RXUNICASTFRAMES_G_OFST 0x1c4
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#define DW_EMAC_DMAGRP_BUS_MODE_OFST 0x1000
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#define DW_EMAC_DMAGRP_TRANSMIT_POLL_DEMAND_OFST 0x1004
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#define DW_EMAC_DMAGRP_RECEIVE_POLL_DEMAND_OFST 0x1008
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#define DW_EMAC_DMAGRP_RECEIVE_DESCRIPTOR_LIST_ADDRESS_OFST 0x100c
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#define DW_EMAC_DMAGRP_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_OFST 0x1010
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#define DW_EMAC_DMAGRP_STATUS_OFST 0x1014
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#define DW_EMAC_DMAGRP_OPERATION_MODE_OFST 0x1018
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#define DW_EMAC_DMAGRP_INTERRUPT_ENABLE_OFST 0x101c
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#define DW_EMAC_DMAGRP_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OFST 0x1020
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#define DW_EMAC_DMAGRP_RECEIVE_INTERRUPT_WATCHDOG_TIMER_OFST 0x1024
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#define DW_EMAC_DMAGRP_AXI_BUS_MODE_OFST 0x1028
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#define DW_EMAC_DMAGRP_AHB_OR_AXI_STATUS_OFST 0x102c
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#define DW_EMAC_DMAGRP_CURRENT_HOST_TRANSMIT_DESCRIPTOR_OFST 0x1048
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#define DW_EMAC_DMAGRP_CURRENT_HOST_RECEIVE_DESCRIPTOR_OFST 0x104c
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#define DW_EMAC_DMAGRP_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_OFST 0x1050
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#define DW_EMAC_DMAGRP_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_OFST 0x1054
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#define DW_EMAC_DMAGRP_HW_FEATURE_OFST 0x1058
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typedef struct {
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UINT32 Tdes0;
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UINT32 Tdes1;
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UINT32 Addr;
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UINT32 AddrNext;
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} DESIGNWARE_HW_DESCRIPTOR;
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typedef struct {
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EFI_PHYSICAL_ADDRESS AddrMap;
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void *Mapping;
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} MAP_INFO;
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typedef struct {
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DESIGNWARE_HW_DESCRIPTOR *TxdescRing[CONFIG_TX_DESCR_NUM];
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DESIGNWARE_HW_DESCRIPTOR *RxdescRing[CONFIG_RX_DESCR_NUM];
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CHAR8 TxBuffer[TX_TOTAL_BUFSIZE];
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CHAR8 RxBuffer[RX_TOTAL_BUFSIZE];
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MAP_INFO TxdescRingMap[CONFIG_TX_DESCR_NUM ];
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MAP_INFO RxdescRingMap[CONFIG_RX_DESCR_NUM ];
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MAP_INFO RxBufNum[CONFIG_TX_DESCR_NUM];
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UINT32 TxCurrentDescriptorNum;
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UINT32 TxNextDescriptorNum;
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UINT32 RxCurrentDescriptorNum;
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UINT32 RxNextDescriptorNum;
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} EMAC_DRIVER;
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VOID
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EFIAPI
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EmacSetMacAddress (
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IN EFI_MAC_ADDRESS *MacAddress,
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IN UINTN MacBaseAddress
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);
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VOID
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EFIAPI
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EmacReadMacAddress (
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OUT EFI_MAC_ADDRESS *MacAddress,
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IN UINTN MacBaseAddress
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);
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EFI_STATUS
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EFIAPI
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EmacDxeInitialization (
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IN EMAC_DRIVER *EmacDriver,
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IN UINTN MacBaseAddress
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);
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EFI_STATUS
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EFIAPI
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EmacDmaInit (
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IN EMAC_DRIVER *EmacDriver,
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IN UINTN MacBaseAddress
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);
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EFI_STATUS
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EFIAPI
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EmacSetupTxdesc (
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IN EMAC_DRIVER *EmacDriver,
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IN UINTN MacBaseAddress
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);
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EFI_STATUS
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EFIAPI
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EmacSetupRxdesc (
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IN EMAC_DRIVER *EmacDriver,
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IN UINTN MacBaseAddress
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);
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VOID
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EFIAPI
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EmacStartTransmission (
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IN UINTN MacBaseAddress
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);
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EFI_STATUS
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EFIAPI
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EmacRxFilters (
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IN UINT32 ReceiveFilterSetting,
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IN BOOLEAN Reset,
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IN UINTN NumMfilter OPTIONAL,
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IN EFI_MAC_ADDRESS *Mfilter OPTIONAL,
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IN UINTN MacBaseAddress
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);
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UINT32
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EFIAPI
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GenEtherCrc32 (
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IN EFI_MAC_ADDRESS *Mac,
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IN UINT32 AddrLen
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);
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UINT8
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EFIAPI
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BitReverse (
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UINT8 Value
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);
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VOID
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EFIAPI
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EmacStopTxRx (
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IN UINTN MacBaseAddress
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);
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EFI_STATUS
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EFIAPI
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EmacDmaStart (
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IN UINTN MacBaseAddress
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);
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VOID
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EFIAPI
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EmacGetDmaStatus (
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OUT UINT32 *IrqStat OPTIONAL,
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IN UINTN MacBaseAddress
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);
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VOID
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EFIAPI
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EmacGetStatistic (
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IN EFI_NETWORK_STATISTICS *Stats,
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IN UINTN MacBaseAddress
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);
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VOID
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EFIAPI
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EmacConfigAdjust (
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IN UINT32 Speed,
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IN UINT32 Duplex,
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IN UINTN MacBaseAddress
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);
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#endif // EMAC_DXE_UTIL_H__
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