/** @file
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PCI Host Bridge Library instance for Socionext SynQuacer ARM SOC
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Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <PiDxe.h>
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#include <IndustryStandard/Pci22.h>
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#include <Library/ArmLib.h>
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#include <Library/DebugLib.h>
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#include <Library/IoLib.h>
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#include <Library/PcdLib.h>
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#include <Library/PciHostBridgeLib.h>
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#include <Library/UefiBootServicesTableLib.h>
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#include <Platform/Pcie.h>
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#include <Platform/VarStore.h>
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#include <Protocol/PciHostBridgeResourceAllocation.h>
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#define IATU_VIEWPORT_OFF 0x900
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#define IATU_VIEWPORT_INBOUND BIT31
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#define IATU_VIEWPORT_OUTBOUND 0
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#define IATU_VIEWPORT_REGION_INDEX(Idx) ((Idx) & 7)
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#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0 0x904
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#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM 0x0
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#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_IO 0x2
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#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG0 0x4
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#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG1 0x5
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#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH BIT12
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#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0 0x908
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#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN BIT31
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#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE BIT28
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#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_32BIT 0xF
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#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_64BIT 0xFF
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#define IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0 0x90C
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#define IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0 0x910
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#define IATU_LIMIT_ADDR_OFF_OUTBOUND_0 0x914
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#define IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0 0x918
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#define IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0 0x91C
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#define CORE_CONTROL 0x000
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#define APP_LTSSM_ENABLE BIT4
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#define DEVICE_TYPE (BIT3 | BIT2 | BIT1 | BIT0)
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#define AXI_CLK_STOP 0x004
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#define DBI_ACLK_STOP BIT8
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#define SLV_ACLK_STOP BIT4
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#define MSTR_ACLK_STOP BIT0
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#define DBI_CSYSREQ_REG BIT9
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#define SLV_CSYSREQ_REG BIT5
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#define MSTR_CSYSREQ_REG BIT1
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#define RESET_CONTROL_1 0x00C
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#define PERST_N_O_REG BIT5
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#define PERST_N_I_REG BIT4
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#define BUTTON_RST_N_REG BIT1
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#define PWUP_RST_N_REG BIT0
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#define RESET_CONTROL_2 0x010
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#define RESET_SELECT_1 0x014
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#define SQU_RST_SEL BIT29
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#define PHY_RST_SEL BIT28
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#define PWR_RST_SEL BIT24
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#define STI_RST_SEL BIT20
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#define N_STI_RST_SEL BIT16
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#define CORE_RST_SEL BIT12
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#define PERST_SEL BIT4
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#define BUTTON_RST_SEL BIT1
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#define PWUP_RST_SEL BIT0
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#define RESET_SELECT_2 0x018
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#define DBI_ARST_SEL BIT8
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#define SLV_ARST_SEL BIT4
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#define MSTR_ARST_SEL BIT0
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#define EM_CONTROL 0x030
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#define PRE_DET_STT_REG BIT4
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#define EM_SELECT 0x034
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#define PRE_DET_STT_SEL BIT4
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#define PM_CONTROL_2 0x050
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#define SYS_AUX_PWR_DET BIT8
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#define PHY_CONFIG_COM_6 0x114
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#define PIPE_PORT_SEL (BIT1 | BIT0)
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#define LINK_MONITOR 0x210
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#define SMLH_LINK_UP BIT0
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#define LINK_CAPABILITIES_REG 0x07C
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#define PCIE_CAP_MAX_LINK_WIDTH (BIT7 | BIT6 | BIT5 | BIT4)
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#define PCIE_CAP_MAX_LINK_SPEED (BIT3 | BIT2 | BIT1 | BIT0)
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#define LINK_CONTROL_LINK_STATUS_REG 0x080
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#define PCIE_CAP_NEGO_LINK_WIDTH (BIT23 | BIT22 | BIT21 | BIT20)
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#define PCIE_CAP_LINK_SPEED (BIT19 | BIT18 | BIT17 | BIT16)
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#define TYPE1_CLASS_CODE_REV_ID_REG 0x008
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#define BASE_CLASS_CODE 0xFF000000
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#define BASE_CLASS_CODE_VALUE 0x06
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#define SUBCLASS_CODE 0x00FF0000
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#define SUBCLASS_CODE_VALUE 0x04
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#define PROGRAM_INTERFACE 0x0000FF00
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#define PROGRAM_INTERFACE_VALUE 0x00
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#define GEN2_CONTROL_OFF 0x80c
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#define DIRECT_SPEED_CHANGE BIT17
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#define MISC_CONTROL_1_OFF 0x8BC
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#define DBI_RO_WR_EN BIT0
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extern PCI_ROOT_BRIDGE mPciRootBridges[];
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STATIC
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VOID
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ConfigureWindow (
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IN EFI_PHYSICAL_ADDRESS DbiBase,
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IN UINTN Index,
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IN UINT64 CpuBase,
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IN UINT64 PciBase,
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IN UINT64 Size,
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IN UINTN Type,
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IN UINTN EnableFlags
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)
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{
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ArmDataMemoryBarrier ();
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MmioWrite32 (DbiBase + IATU_VIEWPORT_OFF,
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IATU_VIEWPORT_OUTBOUND | IATU_VIEWPORT_REGION_INDEX (Index));
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ArmDataMemoryBarrier ();
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MmioWrite32 (DbiBase + IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0,
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(UINT32)(CpuBase & 0xFFFFFFFF));
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MmioWrite32 (DbiBase + IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0,
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(UINT32)(CpuBase >> 32));
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MmioWrite32 (DbiBase + IATU_LIMIT_ADDR_OFF_OUTBOUND_0,
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(UINT32)(CpuBase + Size - 1));
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MmioWrite32 (DbiBase + IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0,
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(UINT32)(PciBase & 0xFFFFFFFF));
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MmioWrite32 (DbiBase + IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0,
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(UINT32)(PciBase >> 32));
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MmioWrite32 (DbiBase + IATU_REGION_CTRL_1_OFF_OUTBOUND_0,
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Type);
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MmioWrite32 (DbiBase + IATU_REGION_CTRL_2_OFF_OUTBOUND_0,
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IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN | EnableFlags);
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}
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STATIC
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VOID
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SnPcieSetData (
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EFI_PHYSICAL_ADDRESS Base,
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UINT32 Offset,
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UINT32 Mask,
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UINT32 In
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)
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{
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UINT32 Data;
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UINT32 Shift;
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Shift = 1;
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if (In) {
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while (!(Mask & Shift))
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Shift <<= 1;
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Data = (MmioRead32 (Base + Offset) & ~Mask) | (In * Shift);
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} else {
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Data = MmioRead32 (Base + Offset) & ~Mask;
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}
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MmioWrite32 (Base + Offset, Data);
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ArmDataMemoryBarrier ();
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}
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STATIC
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UINT32
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SnPcieReadData (
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EFI_PHYSICAL_ADDRESS Base,
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UINT32 Offset,
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UINT32 Mask
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)
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{
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UINT32 Shift;
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Shift = 0;
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while (!(Mask & 1)) {
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Mask >>= 1;
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Shift++;
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}
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ArmDataMemoryBarrier ();
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return (MmioRead32 (Base + Offset) >> Shift) & Mask;
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}
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STATIC
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VOID
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SnDbiRoWrEn (
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IN EFI_PHYSICAL_ADDRESS DbiBase,
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IN INTN MaxLinkWidth,
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IN INTN MaxLinkSpeed
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)
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{
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SnPcieSetData (DbiBase, MISC_CONTROL_1_OFF, DBI_RO_WR_EN, 1);
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SnPcieSetData (DbiBase, LINK_CAPABILITIES_REG, PCIE_CAP_MAX_LINK_WIDTH, MaxLinkWidth);
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SnPcieSetData (DbiBase, LINK_CAPABILITIES_REG, PCIE_CAP_MAX_LINK_SPEED, MaxLinkSpeed);
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SnPcieSetData (DbiBase, TYPE1_CLASS_CODE_REV_ID_REG, BASE_CLASS_CODE, BASE_CLASS_CODE_VALUE);
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SnPcieSetData (DbiBase, TYPE1_CLASS_CODE_REV_ID_REG, SUBCLASS_CODE, SUBCLASS_CODE_VALUE);
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SnPcieSetData (DbiBase, TYPE1_CLASS_CODE_REV_ID_REG, PROGRAM_INTERFACE, PROGRAM_INTERFACE_VALUE);
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SnPcieSetData (DbiBase, MISC_CONTROL_1_OFF, DBI_RO_WR_EN, 0);
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}
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STATIC
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VOID
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PciInitControllerPre (
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IN EFI_PHYSICAL_ADDRESS ExsBase
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)
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{
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SnPcieSetData (ExsBase, EM_SELECT, PRE_DET_STT_SEL, 0);
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SnPcieSetData (ExsBase, EM_CONTROL, PRE_DET_STT_REG, 0);
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SnPcieSetData (ExsBase, EM_CONTROL, PRE_DET_STT_REG, 1);
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// 1: Assert all PHY / LINK resets
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SnPcieSetData (ExsBase, RESET_SELECT_1 , PERST_SEL , 0);
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SnPcieSetData (ExsBase, RESET_CONTROL_1, PERST_N_I_REG , 0);
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SnPcieSetData (ExsBase, RESET_CONTROL_1, PERST_N_O_REG , 0);
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// Device Reset(PERST#) is effective afrer Set device_type (RC)
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SnPcieSetData (ExsBase, RESET_SELECT_1 , PWUP_RST_SEL , 0);
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SnPcieSetData (ExsBase, RESET_CONTROL_1, PWUP_RST_N_REG, 0);
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SnPcieSetData (ExsBase, RESET_SELECT_1 , BUTTON_RST_SEL , 0);
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SnPcieSetData (ExsBase, RESET_CONTROL_1, BUTTON_RST_N_REG, 0);
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SnPcieSetData (ExsBase, RESET_SELECT_1 , PWR_RST_SEL , 1);
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SnPcieSetData (ExsBase, RESET_SELECT_2 , MSTR_ARST_SEL , 1);
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SnPcieSetData (ExsBase, RESET_SELECT_2 , SLV_ARST_SEL , 1);
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SnPcieSetData (ExsBase, RESET_SELECT_2 , DBI_ARST_SEL , 1);
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SnPcieSetData (ExsBase, RESET_SELECT_1 , CORE_RST_SEL , 1);
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SnPcieSetData (ExsBase, RESET_SELECT_1 , STI_RST_SEL , 1);
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SnPcieSetData (ExsBase, RESET_SELECT_1 , N_STI_RST_SEL , 1);
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SnPcieSetData (ExsBase, RESET_SELECT_1 , SQU_RST_SEL , 1);
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SnPcieSetData (ExsBase, RESET_SELECT_1 , PHY_RST_SEL , 1);
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// 2: Set P<n>_app_ltssm_enable='0' for reprogramming before linkup.
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SnPcieSetData (ExsBase, CORE_CONTROL, APP_LTSSM_ENABLE, 0);
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// 3: Set device_type (RC)
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SnPcieSetData (ExsBase, CORE_CONTROL, DEVICE_TYPE, 4);
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}
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STATIC
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VOID
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PciInitControllerPost (
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IN EFI_PHYSICAL_ADDRESS ExsBase,
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IN EFI_PHYSICAL_ADDRESS DbiBase,
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IN EFI_PHYSICAL_ADDRESS ConfigBase,
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IN EFI_PHYSICAL_ADDRESS IoMemBase,
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IN CONST PCI_ROOT_BRIDGE *RootBridge,
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IN BOOLEAN EnableGen2Speed
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)
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{
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// 4: Set Bifurcation 1=disable 4=able
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// 5: Supply Reference (It has executed)
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// 6: Wait for 10usec (Reference Clocks is stable)
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// 7 De assert PERST# */
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SnPcieSetData (ExsBase, RESET_CONTROL_1, PERST_N_I_REG, 1);
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SnPcieSetData (ExsBase, RESET_CONTROL_1, PERST_N_O_REG, 1);
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// 8 Assert SYS_AUX_PWR_DET
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SnPcieSetData(ExsBase, PM_CONTROL_2, SYS_AUX_PWR_DET, 1);
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// 9 Supply following clocks
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SnPcieSetData (ExsBase, AXI_CLK_STOP, MSTR_CSYSREQ_REG, 1);
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SnPcieSetData (ExsBase, AXI_CLK_STOP, MSTR_ACLK_STOP, 0);
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SnPcieSetData (ExsBase, AXI_CLK_STOP, SLV_CSYSREQ_REG, 1);
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SnPcieSetData (ExsBase, AXI_CLK_STOP, SLV_ACLK_STOP, 0);
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SnPcieSetData (ExsBase, AXI_CLK_STOP, DBI_CSYSREQ_REG, 1);
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SnPcieSetData (ExsBase, AXI_CLK_STOP, DBI_ACLK_STOP, 0);
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// 10 De assert PHY reset
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// 11 De assert LINK's PMC reset
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SnPcieSetData (ExsBase, RESET_CONTROL_1, PWUP_RST_N_REG, 1);
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SnPcieSetData (ExsBase, RESET_CONTROL_1, BUTTON_RST_N_REG, 1);
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// 12 PHY auto
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// 13 Wrapper auto
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// 14-17 PHY auto
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// 18 Wrapper auto
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// 19 Update registers through DBI AXI Slave interface
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SnDbiRoWrEn (DbiBase, 4 /* lanes */, /* Gen */ 2);
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//
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// ECAM shift mode uses bits [27:12] of the untranslated address as
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// B/D/F identifiers. This only works as expected if the base of the
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// region is aligned to 256 MB, or the effective bus numbers will be
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// out of sync with the bus base and limit values we chose.
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//
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ASSERT ((ConfigBase % SIZE_256MB) == RootBridge->Bus.Base * SIZE_1MB);
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MmioOr32 (DbiBase + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_IO_SPACE |
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EFI_PCI_COMMAND_MEMORY_SPACE |
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EFI_PCI_COMMAND_BUS_MASTER);
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if (EnableGen2Speed) {
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// Force link speed change to Gen2 at link up
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MmioOr32 (DbiBase + GEN2_CONTROL_OFF, DIRECT_SPEED_CHANGE);
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}
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// Region 0: MMIO32 range
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ConfigureWindow (DbiBase, 0,
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RootBridge->Mem.Base - RootBridge->Mem.Translation,
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RootBridge->Mem.Base,
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RootBridge->Mem.Limit - RootBridge->Mem.Base + 1,
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IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM |
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IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH,
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IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_32BIT);
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// Region 1: Type 0 config space
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ConfigureWindow (DbiBase, 1,
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ConfigBase + RootBridge->Bus.Base * SIZE_1MB,
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0x0,
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SIZE_64KB,
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IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG0,
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IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE);
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// Region 2: Type 1 config space
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ConfigureWindow (DbiBase, 2,
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ConfigBase + RootBridge->Bus.Base * SIZE_1MB + SIZE_64KB,
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0x0,
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(RootBridge->Bus.Limit - RootBridge->Bus.Base + 1) * SIZE_1MB - SIZE_64KB,
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IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG1,
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IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE);
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// Region 3: port I/O range
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ConfigureWindow (DbiBase, 3,
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IoMemBase,
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RootBridge->Io.Base,
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RootBridge->Io.Limit - RootBridge->Io.Base + 1,
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IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_IO,
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0);
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// Region 4: MMIO64 range
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if (RootBridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_MEM64_DECODE) {
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ConfigureWindow (DbiBase, 4,
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RootBridge->MemAbove4G.Base,
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RootBridge->MemAbove4G.Base,
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RootBridge->MemAbove4G.Limit - RootBridge->MemAbove4G.Base + 1,
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IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM |
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IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH,
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IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_32BIT);
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}
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// enable link
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if (SnPcieReadData (ExsBase, CORE_CONTROL, APP_LTSSM_ENABLE) == 0) {
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SnPcieSetData (ExsBase, CORE_CONTROL, APP_LTSSM_ENABLE, 1);
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}
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}
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STATIC CONST struct {
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EFI_PHYSICAL_ADDRESS DbiBase;
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EFI_PHYSICAL_ADDRESS ExsBase;
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EFI_PHYSICAL_ADDRESS ConfigBase;
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EFI_PHYSICAL_ADDRESS IoMemBase;
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} mBaseAddresses [] = {
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{
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SYNQUACER_PCI_SEG0_DBI_BASE,
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SYNQUACER_PCI_SEG0_EXS_BASE,
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SYNQUACER_PCI_SEG0_CONFIG_BASE,
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SYNQUACER_PCI_SEG0_PORTIO_MEMBASE
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},
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{
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SYNQUACER_PCI_SEG1_DBI_BASE,
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SYNQUACER_PCI_SEG1_EXS_BASE,
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SYNQUACER_PCI_SEG1_CONFIG_BASE,
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SYNQUACER_PCI_SEG1_PORTIO_MEMBASE
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},
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};
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EFI_STATUS
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EFIAPI
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SynQuacerPciHostBridgeLibConstructor (
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IN EFI_HANDLE ImageHandle,
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IN EFI_SYSTEM_TABLE *SystemTable
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)
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{
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UINTN Idx;
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UINT64 SettingsVal;
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SYNQUACER_PLATFORM_VARSTORE_DATA *Settings;
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UINT8 MaxSpeed;
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SettingsVal = PcdGet64 (PcdPlatformSettings);
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Settings = (SYNQUACER_PLATFORM_VARSTORE_DATA *)&SettingsVal;
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for (Idx = 0; Idx < ARRAY_SIZE (mBaseAddresses); Idx++) {
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if (PcdGet8 (PcdPcieEnableMask) & (1 << Idx)) {
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PciInitControllerPre (mBaseAddresses[Idx].ExsBase);
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}
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}
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//
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// The PCIe spec requires that PERST# is asserted for at least 100 ms after
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// the power and clocks have become stable. So let's give a bit or margin,
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// and stall for 150 ms between asserting PERST# on both controllers and
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// de-asserting it again.
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//
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gBS->Stall (150 * 1000);
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for (Idx = 0; Idx < ARRAY_SIZE (mBaseAddresses); Idx++) {
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//
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// Check whether this root port is described by any of our 'slot'
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// definitions, and get the maximum speed if this is the case.
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//
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switch (SYNQUACER_PCI_LOCATION (Idx, 0, 0)) {
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case SYNQUACER_PCI_SLOT0_LOCATION:
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MaxSpeed = Settings->PcieSlot0MaxSpeed;
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break;
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case SYNQUACER_PCI_SLOT1_LOCATION:
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MaxSpeed = Settings->PcieSlot1MaxSpeed;
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break;
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case SYNQUACER_PCI_SLOT2_LOCATION:
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MaxSpeed = Settings->PcieSlot2MaxSpeed;
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break;
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default:
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MaxSpeed = PCIE_MAX_SPEED_UNLIMITED;
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}
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if (PcdGet8 (PcdPcieEnableMask) & (1 << Idx)) {
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PciInitControllerPost (mBaseAddresses[Idx].ExsBase,
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mBaseAddresses[Idx].DbiBase,
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mBaseAddresses[Idx].ConfigBase,
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mBaseAddresses[Idx].IoMemBase,
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&mPciRootBridges[Idx],
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(MaxSpeed != PCIE_MAX_SPEED_GEN1));
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}
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}
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return EFI_SUCCESS;
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}
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