/** @file
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SynQuacer DXE platform driver - eMMC support
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Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "PlatformDxe.h"
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// F_SDH30 extended Controller registers
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#define F_SDH30_AHB_CONFIG 0x100
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#define F_SDH30_AHB_BIGED BIT6
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#define F_SDH30_BUSLOCK_DMA BIT5
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#define F_SDH30_BUSLOCK_EN BIT4
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#define F_SDH30_SIN BIT3
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#define F_SDH30_AHB_INCR_16 BIT2
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#define F_SDH30_AHB_INCR_8 BIT1
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#define F_SDH30_AHB_INCR_4 BIT0
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#define F_SDH30_TUNING_SETTING 0x108
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#define F_SDH30_CMD_CHK_DIS BIT16
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#define F_SDH30_IO_CONTROL2 0x114
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#define F_SDH30_MSEL_O_1_8 BIT18
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#define F_SDH30_CRES_O_DN BIT19
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#define F_SDH30_ESD_CONTROL 0x124
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#define F_SDH30_EMMC_RST BIT1
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#define F_SDH30_EMMC_HS200 BIT24
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#define F_SDH30_CMD_DAT_DELAY BIT9
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#define F_SDH30_TUNING_SETTING 0x108
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#define F_SDH30_CMD_CHK_DIS BIT16
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#define F_SDH30_IO_CONTROL2 0x114
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#define F_SDH30_MSEL_O_1_8 BIT18
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#define F_SDH30_CRES_O_DN BIT19
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#define F_SDH30_ESD_CONTROL 0x124
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#define F_SDH30_EMMC_RST BIT1
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#define F_SDH30_EMMC_HS200 BIT24
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#define F_SDH30_CMD_DAT_DELAY BIT9
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#define SD_HC_CLOCK_CTRL 0x2C
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#define SYNQUACER_CLOCK_CTRL_VAL 0xBC01
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#define SD_HC_CAP_SDR104 BIT33
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#define SD_HC_CAP_DDR50 BIT34
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#define ESD_CONTROL_RESET_DELAY (20 * 1000)
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#define IO_CONTROL2_SETTLE_US 3000
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STATIC EFI_HANDLE mSdMmcControllerHandle;
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/**
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Override function for SDHCI capability bits
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@param[in] PassThru A pointer to the
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EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
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@param[in] ControllerHandle The EFI_HANDLE of the controller.
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@param[in] Slot The 0 based slot index.
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@param[in,out] SdMmcHcSlotCapability The SDHCI capability structure.
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@param[in,out] BaseClkFreq The base clock frequency value that
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optionally can be updated.
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@retval EFI_SUCCESS The override function completed successfully.
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@retval EFI_NOT_FOUND The specified controller or slot does not exist.
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@retval EFI_INVALID_PARAMETER SdMmcHcSlotCapability is NULL
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**/
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STATIC
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EFI_STATUS
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EFIAPI
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SynQuacerSdMmcCapability (
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IN EFI_HANDLE ControllerHandle,
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IN UINT8 Slot,
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IN OUT VOID *SdMmcHcSlotCapability,
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IN OUT UINT32 *BaseClkFreq
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)
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{
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UINT64 Capability;
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if (ControllerHandle != mSdMmcControllerHandle) {
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return EFI_SUCCESS;
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}
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ASSERT (Slot == 0);
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//
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// Clear the SDR104 capability bit. This avoids the need for a HS200 tuning
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// quirk that is difficult to support using the generic driver.
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// Clear the DDR50 bit as well to work around an issue with the Kingston
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// EMMC08G-M325-A52 part that was fitted on 96board DeveloperBox samples.
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//
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Capability = ReadUnaligned64 (SdMmcHcSlotCapability);
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Capability &= ~(UINT64)(SD_HC_CAP_SDR104 | SD_HC_CAP_DDR50);
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WriteUnaligned64 (SdMmcHcSlotCapability, Capability);
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return EFI_SUCCESS;
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}
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/**
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Override function for SDHCI controller operations
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@param[in] ControllerHandle The EFI_HANDLE of the controller.
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@param[in] Slot The 0 based slot index.
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@param[in] PhaseType The type of operation and whether the
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hook is invoked right before (pre) or
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right after (post)
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@param[in,out] PhaseData The pointer to a phase-specific data.
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@retval EFI_SUCCESS The override function completed successfully.
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@retval EFI_NOT_FOUND The specified controller or slot does not exist.
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@retval EFI_INVALID_PARAMETER PhaseType is invalid
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**/
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STATIC
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EFI_STATUS
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EFIAPI
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SynQuacerSdMmcNotifyPhase (
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IN EFI_HANDLE ControllerHandle,
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IN UINT8 Slot,
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IN EDKII_SD_MMC_PHASE_TYPE PhaseType,
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IN OUT VOID *PhaseData
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)
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{
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if (ControllerHandle != mSdMmcControllerHandle) {
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return EFI_SUCCESS;
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}
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ASSERT (Slot == 0);
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switch (PhaseType) {
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case EdkiiSdMmcResetPre:
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// Soft reset does not complete unless the clock is already enabled.
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MmioWrite16 (SYNQUACER_EMMC_BASE + SD_HC_CLOCK_CTRL,
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SYNQUACER_CLOCK_CTRL_VAL);
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break;
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case EdkiiSdMmcInitHostPre:
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// init vendor specific regs
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MmioAnd16 (SYNQUACER_EMMC_BASE + F_SDH30_AHB_CONFIG,
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~(F_SDH30_AHB_BIGED | F_SDH30_BUSLOCK_EN));
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MmioOr16 (SYNQUACER_EMMC_BASE + F_SDH30_AHB_CONFIG,
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F_SDH30_SIN | F_SDH30_AHB_INCR_16 | F_SDH30_AHB_INCR_8 |
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F_SDH30_AHB_INCR_4);
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MmioAnd32 (SYNQUACER_EMMC_BASE + F_SDH30_ESD_CONTROL, ~F_SDH30_EMMC_RST);
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MemoryFence ();
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gBS->Stall (ESD_CONTROL_RESET_DELAY);
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MmioOr32 (SYNQUACER_EMMC_BASE + F_SDH30_ESD_CONTROL,
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F_SDH30_EMMC_RST | F_SDH30_CMD_DAT_DELAY | F_SDH30_EMMC_HS200);
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gBS->Stall (IO_CONTROL2_SETTLE_US);
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MmioOr32 (SYNQUACER_EMMC_BASE + F_SDH30_IO_CONTROL2, F_SDH30_CRES_O_DN);
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MemoryFence ();
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MmioOr32 (SYNQUACER_EMMC_BASE + F_SDH30_IO_CONTROL2, F_SDH30_MSEL_O_1_8);
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MemoryFence ();
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MmioAnd32 (SYNQUACER_EMMC_BASE + F_SDH30_IO_CONTROL2, ~F_SDH30_CRES_O_DN);
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MemoryFence ();
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gBS->Stall (IO_CONTROL2_SETTLE_US);
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MmioOr32 (SYNQUACER_EMMC_BASE + F_SDH30_TUNING_SETTING,
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F_SDH30_CMD_CHK_DIS);
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break;
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default:
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break;
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}
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return EFI_SUCCESS;
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}
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STATIC EDKII_SD_MMC_OVERRIDE mSdMmcOverride = {
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EDKII_SD_MMC_OVERRIDE_PROTOCOL_VERSION,
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SynQuacerSdMmcCapability,
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SynQuacerSdMmcNotifyPhase,
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};
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EFI_STATUS
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EFIAPI
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RegisterEmmc (
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VOID
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)
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{
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EFI_STATUS Status;
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EFI_HANDLE Handle;
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Status = RegisterNonDiscoverableMmioDevice (
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NonDiscoverableDeviceTypeSdhci,
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NonDiscoverableDeviceDmaTypeCoherent,
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NULL,
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&mSdMmcControllerHandle,
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1,
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SYNQUACER_EMMC_BASE, SYNQUACER_EMMC_BASE_SZ);
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ASSERT_EFI_ERROR (Status);
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Handle = NULL;
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Status = gBS->InstallProtocolInterface (&Handle,
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&gEdkiiSdMmcOverrideProtocolGuid,
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EFI_NATIVE_INTERFACE, (VOID **)&mSdMmcOverride);
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ASSERT_EFI_ERROR (Status);
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return EFI_SUCCESS;
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}
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