/** @file
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Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR>
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Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "ogma_config.h"
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#include "ogma_internal.h"
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#include "ogma_basic_access.h"
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#include "ogma_misc_internal.h"
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#include <Library/IoLib.h>
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ogma_global_t ogma_global = {
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OGMA_FALSE,
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0,
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NULL
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};
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static const ogma_uint32 hw_ver_reg_addr = OGMA_REG_ADDR_HW_VER;
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static const ogma_uint32 mc_ver_reg_addr = OGMA_REG_ADDR_MC_VER;
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static const ogma_uint32 desc_ring_irq_status_reg_addr[OGMA_DESC_RING_ID_MAX + 1] = {
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OGMA_REG_ADDR_NRM_TX_STATUS,
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OGMA_REG_ADDR_NRM_RX_STATUS,
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};
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static const ogma_uint32 desc_ring_config_reg_addr[OGMA_DESC_RING_ID_MAX + 1] = {
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OGMA_REG_ADDR_NRM_TX_CONFIG,
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OGMA_REG_ADDR_NRM_RX_CONFIG,
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};
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/* Internal function definition*/
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#ifndef OGMA_CONFIG_DISABLE_CLK_CTRL
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STATIC void ogma_set_clk_en_reg (
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ogma_ctrl_t *ctrl_p
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);
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#endif /* OGMA_CONFIG_DISABLE_CLK_CTRL */
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STATIC void ogma_global_init ( void);
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STATIC ogma_err_t ogma_probe_hardware (
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void *base_addr
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);
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STATIC void ogma_reset_hardware (
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ogma_ctrl_t *ctrl_p
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);
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STATIC void ogma_set_microcode(
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ogma_ctrl_t *ctrl_p,
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const void *dma_hm_mc_addr,
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ogma_uint32 dma_hm_mc_len,
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const void *dma_mh_mc_addr,
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ogma_uint32 dma_mh_mc_len,
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const void *pktc_mc_addr,
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ogma_uint32 pktc_mc_len
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);
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STATIC ogma_uint32 ogma_calc_pkt_ctrl_reg_param (
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const ogma_pkt_ctrl_param_t *pkt_ctrl_param_p
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);
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STATIC void ogma_internal_terminate (
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ogma_ctrl_t *ctrl_p
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);
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#ifdef OGMA_CONFIG_DISABLE_CLK_CTRL
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#define ogma_set_clk_en_reg( ctrl_p)
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#else /* OGMA_CONFIG_DISABLE_CLK_CTRL */
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STATIC void ogma_set_clk_en_reg (
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ogma_ctrl_t *ctrl_p
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)
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{
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ogma_uint32 value = 0;
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if ( ctrl_p->clk_ctrl.mac_req_num != 0) {
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value |= OGMA_CLK_EN_REG_DOM_G;
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}
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ogma_write_reg( ctrl_p, OGMA_REG_ADDR_CLK_EN, value);
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}
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#endif /* OGMA_CONFIG_DISABLE_CLK_CTRL */
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void ogma_push_clk_req (
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ogma_ctrl_t *ctrl_p,
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ogma_uint32 domain
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)
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{
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pfdep_hard_lock_ctx_t clk_ctrl_hard_lock_ctx;
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pfdep_acquire_hard_lock (
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&ctrl_p->clk_ctrl_hard_lock,
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&clk_ctrl_hard_lock_ctx);
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if ( ( domain & OGMA_CLK_EN_REG_DOM_G) != 0) {
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++ctrl_p->clk_ctrl.mac_req_num;
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}
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ogma_set_clk_en_reg( ctrl_p);
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pfdep_release_hard_lock(
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&ctrl_p->clk_ctrl_hard_lock,
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&clk_ctrl_hard_lock_ctx);
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}
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void ogma_pop_clk_req(
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ogma_ctrl_t *ctrl_p,
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ogma_uint32 domain
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)
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{
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pfdep_hard_lock_ctx_t clk_ctrl_hard_lock_ctx;
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pfdep_acquire_hard_lock(
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&ctrl_p->clk_ctrl_hard_lock,
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&clk_ctrl_hard_lock_ctx);
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if ( ( domain & OGMA_CLK_EN_REG_DOM_G) != 0) {
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--ctrl_p->clk_ctrl.mac_req_num;
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}
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ogma_set_clk_en_reg( ctrl_p);
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pfdep_release_hard_lock(
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&ctrl_p->clk_ctrl_hard_lock,
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&clk_ctrl_hard_lock_ctx);
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}
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/* Internal function */
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STATIC void ogma_global_init ( void)
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{
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ogma_global.valid_flag = OGMA_TRUE;
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}
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STATIC ogma_err_t ogma_probe_hardware (
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void *base_addr
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)
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{
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ogma_uint32 value;
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/* Read HW_VER Register */
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value = pfdep_iomem_read((void *)
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((pfdep_cpu_addr_t)base_addr +
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(OGMA_REG_ADDR_HW_VER << 2)));
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if ( value != OGMA_VER_NETSEC) {
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pfdep_print(PFDEP_DEBUG_LEVEL_WARNING,
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"Hardware version check warning. Actual:0x%08x, Expected:0x%08x\n",
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(unsigned int)value,
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(unsigned int)OGMA_VER_NETSEC);
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}
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if ( OGMA_VER_MAJOR_NUM(value) != OGMA_VER_MAJOR_NUM(OGMA_VER_NETSEC) ) {
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pfdep_print(PFDEP_DEBUG_LEVEL_FATAL,
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"Hardware Major version check failed. Actual:0x%08x, Expected:0x%08x\n",
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(unsigned int)OGMA_VER_MAJOR_NUM(value),
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(unsigned int)OGMA_VER_MAJOR_NUM(OGMA_VER_NETSEC) );
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return OGMA_ERR_NOTAVAIL;
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}
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/* Print hardware version information. */
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pfdep_print(PFDEP_DEBUG_LEVEL_NOTICE,
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"NETSEC found. Hardware version: %08x\n",
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value);
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return OGMA_ERR_OK;
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}
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STATIC void ogma_reset_hardware (
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ogma_ctrl_t *ctrl_p
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)
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{
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ogma_write_reg( ctrl_p,
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OGMA_REG_ADDR_CLK_EN,
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OGMA_CLK_EN_REG_DOM_ALL);
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/*
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* Stop dma engines if cores are enabled
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*/
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if (ogma_read_reg(ctrl_p, OGMA_REG_ADDR_DIS_CORE) == 0) {
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ogma_write_reg( ctrl_p,
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OGMA_REG_ADDR_DMA_HM_CTRL,
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OGMA_DMA_CTRL_REG_STOP);
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ogma_write_reg( ctrl_p,
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OGMA_REG_ADDR_DMA_MH_CTRL,
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OGMA_DMA_CTRL_REG_STOP);
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while ( ( ogma_read_reg( ctrl_p, OGMA_REG_ADDR_DMA_HM_CTRL)
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& OGMA_DMA_CTRL_REG_STOP) != 0) {
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;
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}
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while ( ( ogma_read_reg( ctrl_p, OGMA_REG_ADDR_DMA_MH_CTRL)
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& OGMA_DMA_CTRL_REG_STOP) != 0) {
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;
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}
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}
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if ( ctrl_p->param.use_gmac_flag) {
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/* Reset F_GMAC4MT */
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ogma_set_mac_reg( ctrl_p,
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OGMA_GMAC_REG_ADDR_BMR,
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OGMA_GMAC_BMR_REG_RESET);
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}
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ogma_write_reg( ctrl_p,
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OGMA_REG_ADDR_SOFT_RST,
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OGMA_SOFT_RST_REG_RESET);
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ogma_write_reg( ctrl_p,
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OGMA_REG_ADDR_SOFT_RST,
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OGMA_SOFT_RST_REG_RUN);
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ogma_write_reg( ctrl_p,
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OGMA_REG_ADDR_COM_INIT,
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OGMA_COM_INIT_REG_ALL);
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while (ogma_read_reg(ctrl_p, OGMA_REG_ADDR_COM_INIT) != 0) {
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;
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}
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if ( ctrl_p->param.use_gmac_flag) {
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/* MAC desc init */
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ogma_write_reg( ctrl_p,
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OGMA_REG_ADDR_MAC_DESC_INIT,
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OGMA_MAC_DESC_INIT_REG_INIT);
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/* Wait MAC desc init done */
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while ( ( ogma_read_reg( ctrl_p, OGMA_REG_ADDR_MAC_DESC_INIT)
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& OGMA_MAC_DESC_INIT_REG_INIT) != 0) {
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;
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}
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/* set MAC_INTF_SEL */
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ogma_write_reg( ctrl_p,
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OGMA_REG_ADDR_MAC_INTF_SEL,
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ctrl_p->param.gmac_config.phy_interface);
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}
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}
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#define OGMA_ROUND_UP(numerator,denominator) (((numerator) + (denominator)) - 1 / (denominator))
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STATIC void ogma_set_microcode (
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ogma_ctrl_t *ctrl_p,
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const void *dma_hm_mc_addr,
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ogma_uint32 dma_hm_mc_len,
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const void *dma_mh_mc_addr,
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ogma_uint32 dma_mh_mc_len,
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const void *pktc_mc_addr,
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ogma_uint32 pktc_mc_len
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)
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{
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ogma_uint i;
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const UINT32 *dmac_hm_cmd_data = (const UINT32 *)dma_hm_mc_addr;
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const UINT32 *dmac_mh_cmd_data = (const UINT32 *)dma_mh_mc_addr;
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const UINT32 *core_cmd_data = (const UINT32 *)pktc_mc_addr;
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/* Loads microcodes to microengines. */
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for( i = 0; i < dma_hm_mc_len; i++) {
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UINT32 data = MmioRead32((UINTN)dmac_hm_cmd_data);
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ogma_write_reg( ctrl_p,
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OGMA_REG_ADDR_DMAC_HM_CMD_BUF,
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data );
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dmac_hm_cmd_data++;
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}
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for( i = 0; i < dma_mh_mc_len; i++) {
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UINT32 data = MmioRead32((UINTN)dmac_mh_cmd_data);
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ogma_write_reg( ctrl_p,
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OGMA_REG_ADDR_DMAC_MH_CMD_BUF,
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data );
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dmac_mh_cmd_data++;
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}
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for( i = 0; i < pktc_mc_len; i++) {
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UINT32 data = MmioRead32((UINTN)core_cmd_data);
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ogma_write_reg( ctrl_p,
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OGMA_REG_ADDR_PKTC_CMD_BUF,
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data );
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core_cmd_data++;
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}
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}
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STATIC ogma_uint32 ogma_calc_pkt_ctrl_reg_param (
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const ogma_pkt_ctrl_param_t *pkt_ctrl_param_p
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)
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{
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ogma_uint32 param = 0;
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if ( pkt_ctrl_param_p->log_chksum_er_flag) {
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param |= OGMA_PKT_CTRL_REG_LOG_CHKSUM_ER;
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}
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if ( pkt_ctrl_param_p->log_hd_imcomplete_flag) {
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param |= OGMA_PKT_CTRL_REG_LOG_HD_INCOMPLETE;
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}
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if ( pkt_ctrl_param_p->log_hd_er_flag) {
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param |= OGMA_PKT_CTRL_REG_LOG_HD_ER;
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}
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if ( pkt_ctrl_param_p->drp_no_match_flag) {
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param |= OGMA_PKT_CTRL_REG_DRP_NO_MATCH;
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}
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return param;
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}
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STATIC
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void
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ogma_pre_init_microengine (
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ogma_handle_t ogma_handle
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)
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{
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UINT16 Data;
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/* Remove dormant settings */
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Data = ogma_get_phy_reg (ogma_handle, OGMA_PHY_REG_ADDR_CONTROL) &
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~((1U << OGMA_PHY_CONTROL_REG_POWER_DOWN) |
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(1U << OGMA_PHY_CONTROL_REG_ISOLATE));
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ogma_set_phy_reg (ogma_handle, OGMA_PHY_REG_ADDR_CONTROL, Data);
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while ((ogma_get_phy_reg (ogma_handle, OGMA_PHY_REG_ADDR_CONTROL) &
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((1U << OGMA_PHY_CONTROL_REG_POWER_DOWN) |
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(1U << OGMA_PHY_CONTROL_REG_ISOLATE))) != 0);
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/* Put phy in loopback mode to guarantee RXCLK input */
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Data |= (1U << OGMA_PHY_CONTROL_REG_LOOPBACK);
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ogma_set_phy_reg (ogma_handle, OGMA_PHY_REG_ADDR_CONTROL, Data);
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while ((ogma_get_phy_reg (ogma_handle, OGMA_PHY_REG_ADDR_CONTROL) &
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(1U << OGMA_PHY_CONTROL_REG_LOOPBACK)) == 0);
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}
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STATIC
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void
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ogma_post_init_microengine (
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IN ogma_handle_t ogma_handle
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)
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{
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UINT16 Data;
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/* Get phy back to normal operation */
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Data = ogma_get_phy_reg (ogma_handle, OGMA_PHY_REG_ADDR_CONTROL) &
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~(1U << OGMA_PHY_CONTROL_REG_LOOPBACK);
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ogma_set_phy_reg (ogma_handle, OGMA_PHY_REG_ADDR_CONTROL, Data);
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while ((ogma_get_phy_reg (ogma_handle, OGMA_PHY_REG_ADDR_CONTROL) &
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(1U << OGMA_PHY_CONTROL_REG_LOOPBACK)) != 0);
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Data |= (1U << OGMA_PHY_CONTROL_REG_RESET);
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/* Apply software reset */
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ogma_set_phy_reg (ogma_handle, OGMA_PHY_REG_ADDR_CONTROL, Data);
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while ((ogma_get_phy_reg (ogma_handle, OGMA_PHY_REG_ADDR_CONTROL) &
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(1U << OGMA_PHY_CONTROL_REG_RESET)) != 0);
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}
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ogma_err_t ogma_init (
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void *base_addr,
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pfdep_dev_handle_t dev_handle,
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const ogma_param_t *param_p,
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const void *dma_hm_mc_addr,
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ogma_uint32 dma_hm_mc_len,
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const void *dma_mh_mc_addr,
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ogma_uint32 dma_mh_mc_len,
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const void *pktc_mc_addr,
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ogma_uint32 pktc_mc_len,
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ogma_handle_t *ogma_handle_p
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)
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{
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ogma_int i;
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ogma_uint32 domain = 0, value;
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ogma_err_t ogma_err;
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ogma_ctrl_t *ctrl_p = NULL;
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ogma_bool inten_reg_hard_lock_init_flag = OGMA_FALSE;
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ogma_bool clk_ctrl_hard_lock_init_flag = OGMA_FALSE;
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ogma_bool all_lock_init_done_flag = OGMA_FALSE;
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pfdep_err_t pfdep_err;
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if ( ( param_p == NULL) ||
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( ogma_handle_p == NULL) ) {
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return OGMA_ERR_PARAM;
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}
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if ( ogma_global.list_entry_num + 1 > OGMA_INSTANCE_NUM_MAX) {
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return OGMA_ERR_INVALID;
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}
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if ((! param_p->desc_ring_param[OGMA_DESC_RING_ID_NRM_TX].valid_flag) &&
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(! param_p->desc_ring_param[OGMA_DESC_RING_ID_NRM_RX].valid_flag)) {
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pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
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"An error occurred at ogma_init.\n"
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"Please set invalid packet desc_ring_param valid_flag.\n");
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return OGMA_ERR_DATA;
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}
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if ( param_p->use_gmac_flag) {
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if ( ( param_p->gmac_config.phy_interface !=
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OGMA_PHY_INTERFACE_GMII) &&
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( param_p->gmac_config.phy_interface !=
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OGMA_PHY_INTERFACE_RGMII) &&
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( param_p->gmac_config.phy_interface !=
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OGMA_PHY_INTERFACE_RMII) ) {
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pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
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"An error occurred at ogma_init.\n"
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"Please set phy_interface to valid value.\n");
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return OGMA_ERR_DATA;
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}
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} else {
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pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
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"An error occurred at ogma_init.\n"
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"Please set use_gmac_flag OGMA_TRUE.\n");
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return OGMA_ERR_DATA;
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}
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if ( param_p->phy_addr >= 32) {
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pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
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"Error: phy_addr out of range\n");
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return OGMA_ERR_DATA;
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}
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ogma_err = ogma_probe_hardware( base_addr);
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if ( ogma_err != OGMA_ERR_OK) {
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return ogma_err;
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}
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if ( !ogma_global.valid_flag) {
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ogma_global_init();
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}
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if ( ( ctrl_p = pfdep_malloc( sizeof( ogma_ctrl_t) ) ) == NULL) {
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pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
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"An error occurred at ogma_init.\n"
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"Failed to ogma_handle memory allocation.\n");
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return OGMA_ERR_ALLOC;
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}
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pfdep_memset( ctrl_p, 0, sizeof( ogma_ctrl_t) );
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ctrl_p->base_addr = base_addr;
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ctrl_p->dev_handle = dev_handle;
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pfdep_memcpy( ( void *)&ctrl_p->param,
|
( void *)param_p,
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sizeof( ogma_param_t) );
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/* Initialize hardware lock */
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pfdep_err = pfdep_init_hard_lock( &ctrl_p->inten_reg_hard_lock);
|
if ( pfdep_err != PFDEP_ERR_OK) {
|
pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
|
"An error occurred at ogma_init.\n"
|
"Failed to inten_reg_hard_lock's initialization.\n");
|
ogma_err = OGMA_ERR_ALLOC;
|
goto err;
|
}
|
inten_reg_hard_lock_init_flag = OGMA_TRUE;
|
|
pfdep_err = pfdep_init_hard_lock( &ctrl_p->clk_ctrl_hard_lock);
|
if ( pfdep_err != PFDEP_ERR_OK) {
|
pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
|
"An error occurred at ogma_init.\n"
|
"Failed to clk_ctrl_hard_lock's initialization.\n");
|
ogma_err = OGMA_ERR_ALLOC;
|
goto err;
|
}
|
clk_ctrl_hard_lock_init_flag = OGMA_TRUE;
|
|
all_lock_init_done_flag = OGMA_TRUE;
|
|
pfdep_err = pfdep_dma_malloc( dev_handle,
|
OGMA_DUMMY_DESC_ENTRY_LEN,
|
&ctrl_p->dummy_desc_entry_addr,
|
&ctrl_p->dummy_desc_entry_phys_addr);
|
|
if ( pfdep_err != PFDEP_ERR_OK) {
|
ogma_err = OGMA_ERR_ALLOC;
|
pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
|
"An error occurred at ogma_init.\n"
|
"Failed to dummy_desc_entry's memory allocation.\n");
|
goto err;
|
}
|
|
/* clear dummy desc entry */
|
pfdep_memset( ctrl_p->dummy_desc_entry_addr,
|
0,
|
OGMA_DUMMY_DESC_ENTRY_LEN);
|
|
ogma_reset_hardware( ctrl_p);
|
|
if ( param_p->use_gmac_flag) {
|
domain |= OGMA_CLK_EN_REG_DOM_G;
|
}
|
|
ogma_push_clk_req( ctrl_p, domain);
|
|
/* set PKT_CTRL */
|
value = ogma_calc_pkt_ctrl_reg_param( ¶m_p->pkt_ctrl_param);
|
|
ogma_write_reg( ctrl_p,
|
OGMA_REG_ADDR_PKT_CTRL,
|
value);
|
|
if ( param_p->use_jumbo_pkt_flag) {
|
|
ctrl_p->rx_pkt_buf_len = OGMA_RX_JUMBO_PKT_BUF_LEN;
|
|
value = ogma_read_reg( ctrl_p,
|
OGMA_REG_ADDR_PKT_CTRL);
|
|
value |= OGMA_PKT_CTRL_REG_EN_JUMBO;
|
|
ogma_write_reg( ctrl_p,
|
OGMA_REG_ADDR_PKT_CTRL,
|
value);
|
} else {
|
|
ctrl_p->rx_pkt_buf_len = OGMA_RX_PKT_BUF_LEN;
|
|
}
|
|
/* set pkt desc ring config */
|
for ( i = 0; i <= OGMA_DESC_RING_ID_MAX; i++) {
|
if ( ctrl_p->param.desc_ring_param[i].valid_flag) {
|
value =
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( ctrl_p->param.desc_ring_param[i].tmr_mode_flag <<
|
OGMA_REG_DESC_RING_CONFIG_TMR_MODE) |
|
( ctrl_p->param.desc_ring_param[i].little_endian_flag <<
|
OGMA_REG_DESC_RING_CONFIG_DAT_ENDIAN) ;
|
|
ogma_write_reg( ctrl_p,
|
desc_ring_config_reg_addr[i],
|
value);
|
|
}
|
}
|
|
/* set microengines */
|
ogma_set_microcode(ctrl_p,
|
dma_hm_mc_addr,
|
dma_hm_mc_len,
|
dma_mh_mc_addr,
|
dma_mh_mc_len,
|
pktc_mc_addr,
|
pktc_mc_len);
|
|
/* alloc desc_ring*/
|
for( i = 0; i <= OGMA_DESC_RING_ID_MAX; i++) {
|
ogma_err = ogma_alloc_desc_ring( ctrl_p, (ogma_desc_ring_id_t)i);
|
if ( ogma_err != OGMA_ERR_OK) {
|
pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
|
"An error occurred at ogma_init.\n"
|
"Failed to ring id NO.%d memory allocation.\n",
|
i);
|
goto err;
|
}
|
}
|
|
if ( param_p->desc_ring_param[OGMA_DESC_RING_ID_NRM_RX].valid_flag) {
|
if ( ( ogma_err = ogma_setup_rx_desc_ring(
|
ctrl_p,
|
&ctrl_p->desc_ring[OGMA_DESC_RING_ID_NRM_RX] ) )
|
!= OGMA_ERR_OK) {
|
pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
|
"An error occurred at ogma_init.\n"
|
"Failed to NRM_RX packet memory allocation.\n");
|
goto err;
|
}
|
}
|
|
/* microengines need domain G */
|
ogma_push_clk_req( ctrl_p, OGMA_CLK_EN_REG_DOM_G);
|
|
/* set DMA tmr ctrl*/
|
ogma_write_reg( ctrl_p, OGMA_REG_ADDR_DMA_TMR_CTRL,
|
( ogma_uint32)( ( OGMA_CONFIG_CLK_HZ / OGMA_CLK_MHZ) - 1) );
|
|
/*
|
* Do pre-initialization tasks for microengine
|
*
|
* In particular, we put phy in loopback mode
|
* in order to make sure RXCLK keeps provided to mac
|
* irrespective of phy link status,
|
* which is required for microengine intialization.
|
* This will be disabled once microengine initialization complete.
|
*/
|
ogma_pre_init_microengine (ctrl_p);
|
|
/* start microengines */
|
ogma_write_reg( ctrl_p, OGMA_REG_ADDR_DIS_CORE, 0);
|
|
if ( pfdep_msleep(1) != PFDEP_ERR_OK) {
|
pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
|
"An error occurred at ogma_init.\n"
|
"Failed to waiting for microcode initialize end.\n");
|
ogma_err = OGMA_ERR_INTERRUPT;
|
goto err;
|
}
|
|
/* check microcode load end & start core */
|
value = ogma_read_reg( ctrl_p, OGMA_REG_ADDR_TOP_STATUS);
|
|
if ( ( value & OGMA_TOP_IRQ_REG_ME_START) == 0) {
|
pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
|
"An error occurred at ogma_init.\n"
|
"Failed to microcode loading.\n");
|
ogma_err = OGMA_ERR_INVALID;
|
goto err;
|
}
|
|
/*
|
* Do post-initialization tasks for microengine
|
*
|
* We put phy in normal mode and apply reset.
|
*/
|
ogma_post_init_microengine (ctrl_p);
|
|
/* clear microcode load end status */
|
ogma_write_reg( ctrl_p, OGMA_REG_ADDR_TOP_STATUS,
|
OGMA_TOP_IRQ_REG_ME_START);
|
|
ogma_pop_clk_req( ctrl_p, OGMA_CLK_EN_REG_DOM_G);
|
|
ctrl_p->core_enabled_flag = OGMA_TRUE;
|
|
ctrl_p->next_p = ogma_global.list_head_p;
|
|
ogma_global.list_head_p = ctrl_p;
|
|
++ogma_global.list_entry_num;
|
|
*ogma_handle_p = ctrl_p;
|
|
#if 1
|
{
|
|
#define OGMA_PKT_CTRL_REG_MODE_TAIKI (1UL << 28)
|
#define OGMA_DMA_MH_CTRL_REG_MODE_TRANS (1UL << 20)
|
#define OGMA_TOP_IRQ_REG_MODE_TRANS_COMP (1UL << 4)
|
#define OGMA_MODE_TRANS_COMP_IRQ_T2N (1UL << 19)
|
|
/* Read Pkt ctrl register */
|
value = ogma_read_reg( ctrl_p, OGMA_REG_ADDR_PKT_CTRL);
|
value |= OGMA_PKT_CTRL_REG_MODE_TAIKI;
|
|
/* change to noromal mode */
|
ogma_write_reg( ctrl_p,
|
OGMA_REG_ADDR_DMA_MH_CTRL,
|
OGMA_DMA_MH_CTRL_REG_MODE_TRANS);
|
|
ogma_write_reg( ctrl_p,
|
OGMA_REG_ADDR_PKT_CTRL,
|
value);
|
|
while ((ogma_read_reg(ctrl_p, OGMA_REG_ADDR_MODE_TRANS_COMP_STATUS) &
|
OGMA_MODE_TRANS_COMP_IRQ_T2N) == 0) {
|
;
|
}
|
|
}
|
#endif
|
|
/* Print microcode version information. */
|
pfdep_print(PFDEP_DEBUG_LEVEL_NOTICE,
|
"Microcode version: %08x\n",
|
ogma_read_reg( ctrl_p,
|
mc_ver_reg_addr) );
|
|
return OGMA_ERR_OK;
|
|
err:
|
if ( !all_lock_init_done_flag) {
|
|
|
if ( clk_ctrl_hard_lock_init_flag) {
|
pfdep_uninit_hard_lock( &ctrl_p->clk_ctrl_hard_lock);
|
}
|
|
if ( inten_reg_hard_lock_init_flag) {
|
pfdep_uninit_hard_lock( &ctrl_p->inten_reg_hard_lock);
|
}
|
|
} else {
|
|
ogma_internal_terminate( ctrl_p);
|
|
}
|
|
pfdep_free( ctrl_p);
|
|
return ogma_err;
|
}
|
|
STATIC void ogma_internal_terminate (
|
ogma_ctrl_t *ctrl_p
|
)
|
{
|
ogma_int i;
|
|
ogma_reset_hardware( ctrl_p);
|
|
/* free desc_ring */
|
for( i = 0; i <= OGMA_DESC_RING_ID_MAX; i++) {
|
ogma_free_desc_ring( ctrl_p, &ctrl_p->desc_ring[i] );
|
}
|
|
if ( ctrl_p->dummy_desc_entry_addr != NULL) {
|
pfdep_dma_free( ctrl_p->dev_handle,
|
OGMA_DUMMY_DESC_ENTRY_LEN,
|
ctrl_p->dummy_desc_entry_addr,
|
ctrl_p->dummy_desc_entry_phys_addr);
|
}
|
|
pfdep_uninit_hard_lock ( &ctrl_p->inten_reg_hard_lock);
|
|
|
pfdep_uninit_hard_lock ( &ctrl_p->clk_ctrl_hard_lock);
|
|
}
|
|
void ogma_terminate (
|
ogma_handle_t ogma_handle
|
)
|
{
|
|
ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
|
ogma_ctrl_t *tmp_ctrl_p = NULL, *old_tmp_ctrl_p = NULL;
|
ogma_uint32 domain = 0;
|
|
if ( ( ctrl_p == NULL) ||
|
( ogma_global.list_entry_num == 0) ) {
|
return;
|
}
|
|
pfdep_assert( ogma_global.list_head_p != NULL);
|
|
if ( ctrl_p->param.use_gmac_flag) {
|
domain |= OGMA_CLK_EN_REG_DOM_G;
|
}
|
|
/* pop domain clock */
|
ogma_pop_clk_req( ctrl_p, domain);
|
|
tmp_ctrl_p = ogma_global.list_head_p;
|
|
while(1) {
|
if ( tmp_ctrl_p == NULL) {
|
/* Could not found ctrl_p specified from the list */
|
return;
|
}
|
if ( ctrl_p == tmp_ctrl_p) {
|
if ( old_tmp_ctrl_p != NULL) {
|
old_tmp_ctrl_p->next_p = ctrl_p->next_p;
|
} else {
|
ogma_global.list_head_p = ctrl_p->next_p;
|
}
|
break;
|
}
|
old_tmp_ctrl_p = tmp_ctrl_p;
|
tmp_ctrl_p = tmp_ctrl_p->next_p;
|
}
|
|
ogma_internal_terminate( ctrl_p);
|
|
--ogma_global.list_entry_num;
|
|
pfdep_free( ctrl_p);
|
return;
|
}
|
|
ogma_err_t ogma_enable_top_irq (
|
ogma_handle_t ogma_handle,
|
ogma_uint32 irq_factor
|
)
|
{
|
ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
|
|
|
if ( ctrl_p == NULL) {
|
return OGMA_ERR_PARAM;
|
}
|
|
/* set irq_factor*/
|
ogma_write_reg( ctrl_p, OGMA_REG_ADDR_TOP_INTEN_SET, irq_factor);
|
|
return OGMA_ERR_OK;
|
}
|
|
ogma_err_t ogma_disable_top_irq (
|
ogma_handle_t ogma_handle,
|
ogma_uint32 irq_factor
|
)
|
{
|
ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
|
|
if ( ctrl_p == NULL) {
|
return OGMA_ERR_PARAM;
|
}
|
|
/* clear irq_factor*/
|
ogma_write_reg( ctrl_p, OGMA_REG_ADDR_TOP_INTEN_CLR, irq_factor);
|
|
return OGMA_ERR_OK;
|
}
|
|
ogma_err_t ogma_enable_desc_ring_irq (
|
ogma_handle_t ogma_handle,
|
ogma_desc_ring_id_t ring_id,
|
ogma_uint32 irq_factor
|
)
|
{
|
ogma_err_t ogma_err = OGMA_ERR_OK;
|
ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
|
ogma_desc_ring_t *desc_ring_p;
|
|
pfdep_err_t pfdep_err;
|
pfdep_soft_lock_ctx_t soft_lock_ctx;
|
|
if ( ctrl_p == NULL) {
|
pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
|
"An error occurred at ogma_enable_desc_ring_irq.\n"
|
"Please set valid ogma_handle.\n");
|
return OGMA_ERR_PARAM;
|
}
|
|
if ( ring_id > OGMA_DESC_RING_ID_MAX) {
|
pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
|
"An error occurred at ogma_enable_desc_ring_irq.\n"
|
"Please select ring id number between 0 and %d.\n",
|
OGMA_DESC_RING_ID_MAX);
|
return OGMA_ERR_PARAM;
|
}
|
|
if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
|
pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
|
"An error occurred at ogma_enable_desc_ring_irq.\n"
|
"Please select valid desc ring.\n");
|
return OGMA_ERR_NOTAVAIL;
|
}
|
|
desc_ring_p = &ctrl_p->desc_ring[ring_id];
|
|
/* get soft lock */
|
pfdep_err = pfdep_acquire_soft_lock (
|
&desc_ring_p->soft_lock,
|
&soft_lock_ctx);
|
|
if ( pfdep_err != PFDEP_ERR_OK) {
|
return OGMA_ERR_INTERRUPT;
|
}
|
|
if ( !desc_ring_p->running_flag) {
|
pfdep_release_soft_lock( &desc_ring_p->soft_lock,
|
&soft_lock_ctx);
|
pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
|
"An error occurred at ogma_enable_desc_ring_irq.\n"
|
"Please select running desc ring.\n");
|
return OGMA_ERR_NOTAVAIL;
|
}
|
|
/* set irq_factor*/
|
ogma_write_reg( ctrl_p,
|
desc_ring_irq_inten_set_reg_addr[ring_id],
|
irq_factor);
|
|
/* free soft_lock*/
|
pfdep_release_soft_lock( &desc_ring_p->soft_lock,
|
&soft_lock_ctx);
|
return ogma_err;
|
}
|
|
ogma_err_t ogma_disable_desc_ring_irq (
|
ogma_handle_t ogma_handle,
|
ogma_desc_ring_id_t ring_id,
|
ogma_uint32 irq_factor
|
)
|
{
|
ogma_err_t ogma_err = OGMA_ERR_OK;
|
ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
|
|
if ( ctrl_p == NULL) {
|
pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
|
"An error occurred at ogma_disable_desc_ring_irq.\n"
|
"Please set valid ogma_handle.\n");
|
return OGMA_ERR_PARAM;
|
}
|
|
if ( ring_id > OGMA_DESC_RING_ID_MAX) {
|
pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
|
"An error occurred at ogma_disable_desc_ring_irq.\n"
|
"Please select ring id number between 0 and %d.\n",
|
OGMA_DESC_RING_ID_MAX);
|
return OGMA_ERR_PARAM;
|
}
|
|
if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
|
pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
|
"An error occurred at ogma_disable_desc_ring_irq.\n"
|
"Please select valid desc ring.\n");
|
return OGMA_ERR_NOTAVAIL;
|
}
|
|
/* Clear irq factor*/
|
ogma_write_reg( ctrl_p,
|
desc_ring_irq_inten_clr_reg_addr[ring_id],
|
irq_factor);
|
|
return ogma_err;
|
}
|
|
ogma_err_t ogma_enable_pkt_irq (
|
ogma_handle_t ogma_handle,
|
ogma_uint32 irq_factor
|
)
|
{
|
ogma_err_t ogma_err = OGMA_ERR_OK;
|
ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
|
|
if ( ctrl_p == NULL) {
|
return OGMA_ERR_PARAM;
|
}
|
|
/* set irq_factor*/
|
ogma_write_reg( ctrl_p, OGMA_REG_ADDR_PKT_INTEN_SET,
|
( irq_factor & OGMA_PKT_IRQ_ALL) );
|
|
return ogma_err;
|
}
|
|
ogma_err_t ogma_disable_pkt_irq (
|
ogma_handle_t ogma_handle,
|
ogma_uint32 irq_factor
|
)
|
{
|
ogma_err_t ogma_err = OGMA_ERR_OK;
|
ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
|
|
if ( ctrl_p == NULL) {
|
return OGMA_ERR_PARAM;
|
}
|
|
/* clear irq_factor*/
|
ogma_write_reg( ctrl_p,
|
OGMA_REG_ADDR_PKT_INTEN_CLR,
|
( irq_factor & OGMA_PKT_IRQ_ALL) );
|
|
return ogma_err;
|
}
|
|
|
ogma_uint32 ogma_get_top_irq_enable (
|
ogma_handle_t ogma_handle
|
)
|
{
|
ogma_uint32 value;
|
ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
|
|
if ( ctrl_p == NULL) {
|
pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
|
"An error occurred at ogma_get_top_irq_enable.\n"
|
"Please set valid ogma_handle.\n");
|
return 0;
|
}
|
|
value = ogma_read_reg( ctrl_p, OGMA_REG_ADDR_TOP_INTEN);
|
|
return value;
|
|
}
|
|
|
ogma_uint32 ogma_get_top_irq_status (
|
ogma_handle_t ogma_handle,
|
ogma_bool mask_flag
|
)
|
{
|
ogma_uint32 value;
|
ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
|
|
if ( ctrl_p == NULL) {
|
pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
|
"An error occurred at ogma_get_top_irq_status.\n"
|
"Please set valid ogma_handle.\n");
|
return 0;
|
}
|
|
value = ogma_read_reg( ctrl_p, OGMA_REG_ADDR_TOP_STATUS);
|
|
if ( mask_flag) {
|
value &= ogma_read_reg( ctrl_p, OGMA_REG_ADDR_TOP_INTEN);
|
}
|
|
return value;
|
}
|
|
ogma_err_t ogma_clear_top_irq_status (
|
ogma_handle_t ogma_handle,
|
ogma_uint32 value
|
)
|
{
|
ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
|
|
if ( ctrl_p == NULL) {
|
pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
|
"An error occurred at ogma_clear_top_irq_status.\n"
|
"Please set valid ogma_handle.\n");
|
return OGMA_ERR_PARAM;
|
}
|
|
/* Write clear irq top status */
|
ogma_write_reg( ctrl_p,
|
OGMA_REG_ADDR_TOP_STATUS,
|
|
( value & OGMA_TOP_IRQ_REG_ME_START) );
|
|
return OGMA_ERR_OK;
|
}
|
|
ogma_uint32 ogma_get_desc_ring_irq_enable (
|
ogma_handle_t ogma_handle,
|
ogma_desc_ring_id_t ring_id
|
)
|
{
|
ogma_uint32 value;
|
ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
|
|
if ( ctrl_p == NULL) {
|
pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
|
"An error occurred at ogma_get_desc_ring_irq_enable.\n"
|
"Please set valid ogma_handle.\n");
|
return 0;
|
}
|
|
if ( ring_id > OGMA_DESC_RING_ID_MAX) {
|
pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
|
"An error occurred at ogma_get_desc_ring_irq_enable.\n"
|
"Please select ring id number between 0 and %d.\n",
|
OGMA_DESC_RING_ID_MAX);
|
return 0;
|
}
|
|
if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
|
pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
|
"An error occurred at ogma_get_desc_ring_irq_enable.\n"
|
"Please select valid desc ring.\n");
|
return 0;
|
}
|
|
value = ogma_read_reg( ctrl_p,
|
desc_ring_irq_inten_reg_addr[ring_id] );
|
|
return value;
|
}
|
|
|
ogma_uint32 ogma_get_desc_ring_irq_status (
|
ogma_handle_t ogma_handle,
|
ogma_desc_ring_id_t ring_id,
|
ogma_bool mask_flag
|
)
|
{
|
ogma_uint32 value;
|
ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
|
|
if ( ctrl_p == NULL) {
|
pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
|
"An error occurred at ogma_get_desc_ring_irq_status.\n"
|
"Please set valid ogma_handle.\n");
|
return 0;
|
}
|
|
if ( ring_id > OGMA_DESC_RING_ID_MAX) {
|
pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
|
"An error occurred at ogma_get_desc_ring_irq_status.\n"
|
"Please select ring id number between 0 and %d.\n",
|
OGMA_DESC_RING_ID_MAX);
|
return 0;
|
}
|
|
if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
|
pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
|
"An error occurred at ogma_get_desc_ring_irq_status.\n"
|
"Please select valid desc ring.\n");
|
return 0;
|
}
|
|
value = ogma_read_reg( ctrl_p,
|
desc_ring_irq_status_reg_addr[ring_id] );
|
|
if ( mask_flag) {
|
value &= ogma_read_reg( ctrl_p,
|
desc_ring_irq_inten_reg_addr[ring_id] );
|
}
|
|
return value;
|
}
|
|
|
|
ogma_err_t ogma_clear_desc_ring_irq_status (
|
ogma_handle_t ogma_handle,
|
ogma_desc_ring_id_t ring_id,
|
ogma_uint32 value
|
)
|
{
|
|
ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
|
|
if ( ctrl_p == NULL) {
|
pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
|
"An error occurred at ogma_clear_desc_ring_irq_status.\n"
|
"Please set valid ogma_handle.\n");
|
return OGMA_ERR_PARAM;
|
}
|
|
if ( ring_id > OGMA_DESC_RING_ID_MAX) {
|
pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
|
"An error occurred at ogma_clear_desc_ring_irq_status.\n"
|
"Please select ring id number between 0 and %d.\n",
|
OGMA_DESC_RING_ID_MAX);
|
return OGMA_ERR_PARAM;
|
}
|
|
if ( !ctrl_p->desc_ring[ring_id].param.valid_flag) {
|
pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
|
"An error occurred at ogma_clear_desc_ring_irq_status.\n"
|
"Please select valid desc ring.\n");
|
return OGMA_ERR_NOTAVAIL;
|
}
|
|
/* Write clear descring irq status */
|
ogma_write_reg( ctrl_p,
|
desc_ring_irq_status_reg_addr[ring_id],
|
( value & ( OGMA_CH_IRQ_REG_EMPTY |
|
OGMA_CH_IRQ_REG_ERR) ) );
|
|
return OGMA_ERR_OK;
|
|
}
|
|
|
ogma_uint32 ogma_get_pkt_irq_enable (
|
ogma_handle_t ogma_handle
|
)
|
{
|
ogma_uint32 value;
|
ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
|
|
|
if ( ctrl_p == NULL) {
|
pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
|
"An error occurred at ogma_get_pkt_irq_enable.\n"
|
"Please set valid ogma_handle.\n");
|
return 0;
|
}
|
|
value = ogma_read_reg( ctrl_p, OGMA_REG_ADDR_PKT_INTEN);
|
|
value &= OGMA_PKT_IRQ_ALL;
|
|
return value;
|
|
}
|
|
ogma_uint32 ogma_get_pkt_irq_status (
|
ogma_handle_t ogma_handle,
|
ogma_bool mask_flag
|
)
|
{
|
ogma_uint32 value;
|
ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
|
|
if ( ctrl_p == NULL) {
|
pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
|
"An error occurred at ogma_get_pkt_irq_statusnon_clear.\n"
|
"Please set valid ogma_handle.\n");
|
return 0;
|
}
|
|
value = ogma_read_reg( ctrl_p, OGMA_REG_ADDR_PKT_STATUS);
|
|
if ( mask_flag) {
|
value &= ogma_read_reg( ctrl_p, OGMA_REG_ADDR_PKT_INTEN);
|
}
|
|
return value;
|
}
|
|
ogma_err_t ogma_clear_pkt_irq_status (
|
ogma_handle_t ogma_handle,
|
ogma_uint32 value
|
)
|
{
|
ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
|
|
if ( ctrl_p == NULL) {
|
pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
|
"An error occurred at ogma_clear_pkt_irq_status.\n"
|
"Please set valid ogma_handle.\n");
|
return OGMA_ERR_PARAM;
|
}
|
|
/* Write clear irq pkt status */
|
ogma_write_reg( ctrl_p,
|
OGMA_REG_ADDR_PKT_STATUS,
|
( value & ( ( OGMA_PKT_IRQ_MAC_ER |
|
OGMA_PKT_IRQ_JUMBO_ER |
|
OGMA_PKT_IRQ_CHKSUM_ER |
|
OGMA_PKT_IRQ_HD_INCOMPLETE |
|
OGMA_PKT_IRQ_HD_ER |
|
OGMA_PKT_IRQ_DRP_NO_MATCH) ) ) );
|
|
return OGMA_ERR_OK;
|
}
|
|
#ifdef OGMA_CONFIG_REC_STAT
|
ogma_err_t ogma_get_stat_info (
|
ogma_handle_t ogma_handle,
|
ogma_stat_info_t *stat_info_p,
|
ogma_bool clear_flag
|
)
|
{
|
|
ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
|
|
if ( ( ctrl_p == NULL) || (stat_info_p == NULL) ) {
|
return OGMA_ERR_PARAM;
|
}
|
|
pfdep_memcpy( stat_info_p,
|
&ctrl_p->stat_info,
|
sizeof( ogma_stat_info_t) );
|
|
|
if ( clear_flag) {
|
pfdep_memset( &ctrl_p->stat_info, 0, sizeof( ogma_stat_info_t) );
|
}
|
|
return OGMA_ERR_OK;
|
|
}
|
#endif /* OGMA_CONFIG_REC_STAT */
|
|
ogma_uint32 ogma_get_hw_ver (
|
ogma_handle_t ogma_handle
|
)
|
{
|
ogma_uint32 value;
|
ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
|
|
if ( ctrl_p == NULL) {
|
return 0;
|
}
|
|
value = ogma_read_reg( ctrl_p,
|
hw_ver_reg_addr);
|
|
return value;
|
}
|
|
|
ogma_uint32 ogma_get_mcr_ver (
|
ogma_handle_t ogma_handle
|
)
|
{
|
ogma_uint32 value;
|
ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
|
|
if ( ctrl_p == NULL) {
|
return 0;
|
}
|
|
value = ogma_read_reg( ctrl_p,
|
mc_ver_reg_addr);
|
|
return value;
|
}
|
|
ogma_uint32 ogma_get_mac_irq_enable (
|
ogma_handle_t ogma_handle
|
)
|
{
|
ogma_uint32 value;
|
ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
|
|
if ( ctrl_p == NULL) {
|
pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
|
"An error occurred at ogma_ogma_get_mac_irq_enable.\n"
|
"Please set valid ogma_handle.\n");
|
return 0;
|
}
|
|
value = ogma_read_reg( ctrl_p, OGMA_REG_ADDR_MAC_INTEN);
|
|
|
return value;
|
}
|
|
ogma_uint32 ogma_get_mac_irq_status (
|
ogma_handle_t ogma_handle,
|
ogma_bool mask_flag
|
)
|
{
|
ogma_uint32 value;
|
ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
|
|
if ( ctrl_p == NULL) {
|
pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
|
"An error occurred at ogma_get_mac_irq_status.\n"
|
"Please set valid ogma_handle.\n");
|
return 0;
|
}
|
|
|
value = ogma_read_reg( ctrl_p, OGMA_REG_ADDR_MAC_STATUS);
|
|
if ( mask_flag) {
|
value &= ogma_read_reg( ctrl_p, OGMA_REG_ADDR_MAC_INTEN);
|
}
|
|
|
return value;
|
}
|
|
ogma_err_t ogma_clear_mac_irq_status (
|
ogma_handle_t ogma_handle,
|
ogma_uint32 value
|
)
|
{
|
ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
|
|
if ( ctrl_p == NULL) {
|
pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
|
"An error occurred at ogma_clear_mac_irq_status.\n"
|
"Please set valid ogma_handle.\n");
|
return OGMA_ERR_PARAM;
|
}
|
|
|
/* Commented out because no write-clear bit exists now. */
|
#if 0
|
ogma_write_reg( ctrl_p,
|
OGMA_REG_ADDR_MAC_STATUS,
|
( value & /* T.B.D. */) );
|
#endif
|
|
|
return OGMA_ERR_OK;
|
|
}
|
|
ogma_err_t ogma_enable_mac_irq (
|
ogma_handle_t ogma_handle,
|
ogma_uint32 irq_factor
|
)
|
{
|
ogma_uint32 value;
|
ogma_err_t ogma_err = OGMA_ERR_OK;
|
ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
|
pfdep_hard_lock_ctx_t inten_reg_hard_lock_ctx;
|
|
if ( ctrl_p == NULL) {
|
pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
|
"An error occurred at ogma_enable_mac_irq.\n"
|
"Please set valid ogma_handle.\n");
|
return OGMA_ERR_PARAM;
|
}
|
|
/* get inten_reg_hard_lock */
|
pfdep_acquire_hard_lock( &ctrl_p->inten_reg_hard_lock,
|
&inten_reg_hard_lock_ctx);
|
|
value = ogma_read_reg( ctrl_p,
|
OGMA_REG_ADDR_MAC_INTEN);
|
|
value |= irq_factor;
|
|
ogma_write_reg( ctrl_p,
|
OGMA_REG_ADDR_MAC_INTEN,
|
value);
|
|
|
/* free inten_reg_hard_lock*/
|
pfdep_release_hard_lock( &ctrl_p->inten_reg_hard_lock,
|
&inten_reg_hard_lock_ctx);
|
return ogma_err;
|
}
|
|
ogma_err_t ogma_disable_mac_irq (
|
ogma_handle_t ogma_handle,
|
ogma_uint32 irq_factor
|
)
|
{
|
ogma_uint32 value;
|
ogma_err_t ogma_err = OGMA_ERR_OK;
|
ogma_ctrl_t *ctrl_p = (ogma_ctrl_t *)ogma_handle;
|
|
pfdep_hard_lock_ctx_t inten_reg_hard_lock_ctx;
|
|
|
if ( ctrl_p == NULL) {
|
pfdep_print( PFDEP_DEBUG_LEVEL_FATAL,
|
"An error occurred at ogma_disable_mac_irq.\n"
|
"Please set valid ogma_handle.\n");
|
return OGMA_ERR_PARAM;
|
}
|
|
/* get inten_reg_hard_lock */
|
pfdep_acquire_hard_lock( &ctrl_p->inten_reg_hard_lock,
|
&inten_reg_hard_lock_ctx);
|
|
value = ogma_read_reg( ctrl_p,
|
OGMA_REG_ADDR_MAC_INTEN);
|
|
value &= (~irq_factor);
|
|
ogma_write_reg( ctrl_p,
|
OGMA_REG_ADDR_MAC_INTEN,
|
value);
|
|
|
/* free inten_reg_hard_lock*/
|
pfdep_release_hard_lock( &ctrl_p->inten_reg_hard_lock,
|
&inten_reg_hard_lock_ctx);
|
return ogma_err;
|
|
}
|
