/* SPDX-License-Identifier: BSD-3-Clause */
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/*
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* Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd.
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*/
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#ifndef _HAL_SPI_MEM_H_
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#define _HAL_SPI_MEM_H_
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#define BIT(nr) (1UL << (nr))
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/** SPI Memory host mode */
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#define HAL_SPI_CPHA BIT(0) /**< clock phase */
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#define HAL_SPI_CPOL BIT(1) /**< clock polarity */
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#define HAL_SPI_MODE_0 (0 | 0) /**< (original MicroWire) */
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#define HAL_SPI_MODE_1 (0 | HAL_SPI_CPHA)
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#define HAL_SPI_MODE_2 (HAL_SPI_CPOL | 0)
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#define HAL_SPI_MODE_3 (HAL_SPI_CPOL | HAL_SPI_CPHA)
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#define HAL_SPI_CS_HIGH BIT(2) /**< CS active high */
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#define HAL_SPI_LSB_FIRST BIT(3) /**< per-word bits-on-wire */
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#define HAL_SPI_3WIRE BIT(4) /**< SI/SO signals shared */
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#define HAL_SPI_LOOP BIT(5) /**< loopback mode */
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#define HAL_SPI_SLAVE BIT(6) /**< slave mode */
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#define HAL_SPI_PREAMBLE BIT(7) /**< Skip preamble bytes */
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#define HAL_SPI_TX_BYTE BIT(8) /**< transmit with 1 wire byte */
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#define HAL_SPI_TX_DUAL BIT(9) /**< transmit with 2 wires */
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#define HAL_SPI_TX_QUAD BIT(10) /**< transmit with 4 wires */
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#define HAL_SPI_RX_SLOW BIT(11) /**< receive with 1 wire slow */
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#define HAL_SPI_RX_DUAL BIT(12) /**< receive with 2 wires */
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#define HAL_SPI_RX_QUAD BIT(13) /**< receive with 4 wires */
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#define HAL_SPI_XIP BIT(14) /**< support spi flash xip mode */
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/** SPI Memory host xfer flags */
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#define HAL_SPI_XFER_BEGIN BIT(0) /**< Assert CS before transfer */
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#define HAL_SPI_XFER_END BIT(1) /**< Deassert CS after transfer */
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#define HAL_SPI_XFER_ONCE (HAL_SPI_XFER_BEGIN | HAL_SPI_XFER_END)
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#define JEDEC_MFR(id) (((id) >> 16) & 0xff)
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#define HAL_SPI_MEM_OP_FORMAT(__cmd, __addr, __dummy, __data) \
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{ \
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.cmd = __cmd, \
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.addr = __addr, \
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.dummy = __dummy, \
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.data = __data, \
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}
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#define HAL_SPI_MEM_OP_CMD(__opcode, __buswidth) \
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{ \
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.buswidth = __buswidth, \
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.opcode = __opcode, \
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}
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#define HAL_SPI_MEM_OP_ADDR(__nbytes, __val, __buswidth) \
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{ \
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.nbytes = __nbytes, \
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.val = __val, \
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.buswidth = __buswidth, \
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}
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#define HAL_SPI_MEM_OP_NO_ADDR \
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{ \
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.nbytes = 0, \
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.val = 0, \
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.buswidth = 0, \
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}
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#define HAL_SPI_MEM_OP_DUMMY(__nbytes, __buswidth) \
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{ \
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.a2dIdle = 0, \
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.nbytes = __nbytes, \
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.buswidth = __buswidth, \
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}
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#define HAL_SPI_MEM_OP_NO_DUMMY \
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{ \
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.a2dIdle = 0, \
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.nbytes = 0, \
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.buswidth = 0, \
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}
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#define HAL_SPI_MEM_OP_DATA_IN(__nbytes, __buf, __buswidth) \
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{ \
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.dir = HAL_SPI_MEM_DATA_IN, \
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.nbytes = __nbytes, \
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.buf.in = __buf, \
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.buswidth = __buswidth, \
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}
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#define HAL_SPI_MEM_OP_DATA_OUT(__nbytes, __buf, __buswidth) \
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{ \
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.dir = HAL_SPI_MEM_DATA_OUT, \
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.nbytes = __nbytes, \
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.buf.out = __buf, \
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.buswidth = __buswidth, \
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}
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#define HAL_SPI_MEM_OP_NO_DATA \
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{ \
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.dir = HAL_SPI_MEM_DATA_IN, \
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.nbytes = 0, \
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.buf.out = NULL, \
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.buswidth = 0, \
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}
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/* Max len case: cmd(1) + addr(4) + dummy(4) */
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#define HAL_SPI_OP_LEN_MAX 0x10
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/***************************** Structure Definition **************************/
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enum SPI_MEM_DATA_DIR {
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HAL_SPI_MEM_DATA_IN,
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HAL_SPI_MEM_DATA_OUT,
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};
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struct HAL_SPI_MEM_OP {
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struct {
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uint8_t buswidth;
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uint8_t opcode;
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} cmd;
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struct {
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uint8_t nbytes;
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uint8_t buswidth;
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uint32_t val;
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} addr;
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struct {
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uint8_t a2dIdle;
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uint8_t nbytes;
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uint8_t buswidth;
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} dummy;
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struct {
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uint8_t buswidth;
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enum SPI_MEM_DATA_DIR dir;
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unsigned int nbytes;
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/**< buf.{in,out} must be DMA-able. */
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union {
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void *in;
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const void *out;
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} buf;
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} data;
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};
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#define HAL_SPI_MEM_OP(__cmd, __addr, __dummy, __data) \
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{ \
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.cmd = __cmd, \
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.addr = __addr, \
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.dummy = __dummy, \
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.data = __data, \
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}
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#endif
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