/* SPDX-License-Identifier: BSD-3-Clause */
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/*
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* Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd.
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*/
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#ifndef _HAL_SFC_NOR_H_
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#define _HAL_SFC_NOR_H_
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/***************************** Structure Definition **************************/
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#define SPI_NOR_MAX_CMD_SIZE 8
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#define SNOR_SPEED_MAX 133000000
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#define SNOR_SPEED_DEFAULT 80000000
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#define SNOR_PROTO_STR(a, b, c) (((a) << 8) | ((b) << 4) | (c))
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#define SNOR_GET_PROTOCOL_ADDR_BITS(proto) (((proto) >> 4) & 0xf)
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#define SNOR_GET_PROTOCOL_DATA_BITS(proto) ((proto) & 0xf)
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enum SPI_NOR_PROTOCOL {
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SNOR_PROTO_1_1_1 = SNOR_PROTO_STR(1, 1, 1),
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SNOR_PROTO_1_1_2 = SNOR_PROTO_STR(1, 1, 2),
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SNOR_PROTO_1_1_4 = SNOR_PROTO_STR(1, 1, 4),
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SNOR_PROTO_1_1_8 = SNOR_PROTO_STR(1, 1, 8),
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SNOR_PROTO_1_2_2 = SNOR_PROTO_STR(1, 2, 2),
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SNOR_PROTO_1_4_4 = SNOR_PROTO_STR(1, 4, 4),
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SNOR_PROTO_1_8_8 = SNOR_PROTO_STR(1, 8, 8),
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SNOR_PROTO_2_2_2 = SNOR_PROTO_STR(2, 2, 2),
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SNOR_PROTO_4_4_4 = SNOR_PROTO_STR(4, 4, 4),
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SNOR_PROTO_8_8_8 = SNOR_PROTO_STR(8, 8, 8),
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};
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/* Flash opcodes. */
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#define SPINOR_OP_WREN 0x06 /**< Write enable */
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#define SPINOR_OP_RDSR 0x05 /**< Read status register */
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#define SPINOR_OP_WRSR 0x01 /**< Write status register 1 byte */
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#define SPINOR_OP_RDSR1 0x35 /**< Read status register 1 */
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#define SPINOR_OP_WRSR1 0x31 /**< Write status register 1 */
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#define SPINOR_OP_RDSR2 0x15 /**< Read status register 2 */
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#define SPINOR_OP_WRSR2 0x3e /**< Write status register 2 */
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#define SPINOR_OP_READ 0x03 /**< Read data bytes (low frequency) */
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#define SPINOR_OP_READ_FAST 0x0b /**< Read data bytes (high frequency) */
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#define SPINOR_OP_READ_1_1_2 0x3b /**< Read data bytes (Dual Output SPI) */
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#define SPINOR_OP_READ_1_2_2 0xbb /**< Read data bytes (Dual I/O SPI) */
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#define SPINOR_OP_READ_1_1_4 0x6b /**< Read data bytes (Quad Output SPI) */
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#define SPINOR_OP_READ_1_4_4 0xeb /**< Read data bytes (Quad I/O SPI) */
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#define SPINOR_OP_READ_EC 0xec /**< Read data bytes (Quad I/O SPI) 4 byte address */
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#define SPINOR_OP_PP 0x02 /**< Page program (up to 256 bytes) */
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#define SPINOR_OP_PP_1_1_4 0x32 /**< Quad page program */
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#define SPINOR_OP_PP_1_4_4 0x38 /**< Quad page program */
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#define SPINOR_OP_BE_4K 0x20 /**< Erase 4KiB block */
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#define SPINOR_OP_BE_4K_PMC 0xd7 /**< Erase 4KiB block on PMC chips */
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#define SPINOR_OP_BE_32K 0x52 /**< Erase 32KiB block */
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#define SPINOR_OP_CHIP_ERASE 0xc7 /**< Erase whole flash chip */
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#define SPINOR_OP_SE 0xd8 /**< Sector erase (usually 64KiB) */
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#define SPINOR_OP_RDID 0x9f /**< Read JEDEC ID */
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#define SPINOR_OP_RDSFDP 0x5a /**< Read SFDP */
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#define SPINOR_OP_RDCR 0x15 /**< Read configuration register */
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#define SPINOR_OP_WRCR 0x11 /**< Write configuration register */
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#define SPINOR_OP_RDFSR 0x70 /**< Read flag status register */
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#define SPINOR_OP_CLFSR 0x50 /**< Clear flag status register */
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#define SPINOR_OP_RDEAR 0xc8 /**< Read Extended Address Register */
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#define SPINOR_OP_WREAR 0xc5 /**< Write Extended Address Register */
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#define SPINOR_OP_READ_UUID 0x4b /**< Read SPI Nor UUID */
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#define SPINOR_OP_READ_SFDP 0x5A /**< Read SPI Nor SFDP */
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struct SPI_NOR {
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struct HAL_FSPI_HOST *spi;
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const struct FLASH_INFO *info;
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UINT32 pageSize;
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UINT8 addrWidth;
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UINT8 eraseOpcodeSec;
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UINT8 eraseOpcodeBlk;
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UINT8 readOpcode;
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UINT8 readDummy;
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UINT8 programOpcode;
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enum SPI_NOR_PROTOCOL readProto;
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enum SPI_NOR_PROTOCOL writeProto;
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UINT8 cmdBuf[SPI_NOR_MAX_CMD_SIZE];
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UINT32 size;
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UINT32 sectorSize;
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UINT32 eraseSize;
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};
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typedef enum {
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ERASE_SECTOR = 0,
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ERASE_BLOCK64K,
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ERASE_CHIP
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} NOR_ERASE_TYPE;
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RETURN_STATUS HAL_SNOR_Init(struct SPI_NOR *nor);
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RETURN_STATUS HAL_SNOR_DeInit(struct SPI_NOR *nor);
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UINT32 HAL_SNOR_GetCapacity(struct SPI_NOR *nor);
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RETURN_STATUS HAL_SNOR_ReadID(struct SPI_NOR *nor, UINT8 *data);
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RETURN_STATUS HAL_SNOR_ReadData(struct SPI_NOR *nor, UINT32 from, void *buf, UINT32 len);
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RETURN_STATUS HAL_SNOR_ProgData(struct SPI_NOR *nor, UINT32 to, void *buf, UINT32 len);
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RETURN_STATUS HAL_SNOR_Read(struct SPI_NOR *nor, UINT32 sec, UINT32 nSec, void *pData);
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RETURN_STATUS HAL_SNOR_Write(struct SPI_NOR *nor, UINT32 sec, UINT32 nSec, void *pData);
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RETURN_STATUS HAL_SNOR_OverWrite(struct SPI_NOR *nor, UINT32 sec, UINT32 nSec, void *pData);
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RETURN_STATUS HAL_SNOR_Erase(struct SPI_NOR *nor, UINT32 addr, NOR_ERASE_TYPE EraseType);
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BOOLEAN HAL_SNOR_IsFlashSupported(UINT8 *flashId);
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RETURN_STATUS HAL_SNOR_ReadUUID(struct SPI_NOR *nor, void *buf);
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#endif
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