/** @file
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*
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* Copyright (c) 2022, Rockchip Inc.
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*
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*
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* SPDX-License-Identifier: BSD-2-Clause-Patent
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*
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**/
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#ifndef __PCIE_INIT_H__
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#define __PCIE_INIT_H__
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#include <Library/DebugLib.h>
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#include <Library/BaseLib.h>
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#include <Library/UefiLib.h>
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#include <Library/TimerLib.h>
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#define RK_PCIE_DBG 0
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#ifndef BIT
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#define BIT(nr) (1 << (nr))
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#endif
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#if __SIZEOF_POINTER__ == 8
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#define BITS_PER_LONG 64
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#elif __SIZEOF_POINTER__ == 4
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#define BITS_PER_LONG 32
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#else
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#error "Unexpected __SIZEOF_POINTER__"
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#endif
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#define upper_32_bits(n) ((UINT32)(((n) >> 16) >> 16))
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#define lower_32_bits(n) ((UINT32)(n))
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#define GENMASK(h, l) \
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(((~0UL) - (1UL << (l)) + 1) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
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extern EFI_GUID gEfiPcieRootBridgeProtocolGuid;
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struct rk_pcie {
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UINTN dbi_base;
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UINTN apb_base;
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UINTN cfg_base;
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UINT32 first_busno;
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UINT32 gen;
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UINT32 lane;
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};
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enum {
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PCIBIOS_SUCCESSFUL = 0x0000,
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PCIBIOS_UNSUPPORTED = -1,
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PCIBIOS_NODEV = -2,
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};
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#define msleep(a) MicroSecondDelay(a);
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/* Parameters for the waiting for iATU enabled routine */
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#define PCIE_CLIENT_GENERAL_DEBUG 0x104
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#define PCIE_CLIENT_HOT_RESET_CTRL 0x180
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#define PCIE_LTSSM_ENABLE_ENHANCE BIT(4)
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#define PCIE_CLIENT_LTSSM_STATUS 0x300
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#define SMLH_LINKUP BIT(16)
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#define RDLH_LINKUP BIT(17)
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#define PCIE_CLIENT_DBG_FIFO_MODE_CON 0x310
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#define PCIE_CLIENT_DBG_FIFO_PTN_HIT_D0 0x320
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#define PCIE_CLIENT_DBG_FIFO_PTN_HIT_D1 0x324
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#define PCIE_CLIENT_DBG_FIFO_TRN_HIT_D0 0x328
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#define PCIE_CLIENT_DBG_FIFO_TRN_HIT_D1 0x32c
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#define PCIE_CLIENT_DBG_FIFO_STATUS 0x350
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#define PCIE_CLIENT_DBG_TRANSITION_DATA 0xffff0000
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#define PCIE_CLIENT_DBF_EN 0xffff0003
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/* PCI DBICS registers */
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#define PCIE_LINK_STATUS_REG 0x80
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#define PCIE_LINK_STATUS_SPEED_OFF 16
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#define PCIE_LINK_STATUS_SPEED_MASK (0xf << PCIE_LINK_STATUS_SPEED_OFF)
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#define PCIE_LINK_STATUS_WIDTH_OFF 20
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#define PCIE_LINK_STATUS_WIDTH_MASK (0xf << PCIE_LINK_STATUS_WIDTH_OFF)
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#define PCIE_LINK_CAPABILITY 0x7c
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#define PCIE_LINK_CTL_2 0xa0
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#define TARGET_LINK_SPEED_MASK 0xf
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#define LINK_SPEED_GEN_1 0x1
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#define LINK_SPEED_GEN_2 0x2
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#define LINK_SPEED_GEN_3 0x3
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#define PCIE_MISC_CONTROL_1_OFF 0x8bc
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#define PCIE_DBI_RO_WR_EN BIT(0)
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#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80c
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#define PORT_LOGIC_SPEED_CHANGE BIT(17)
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/*
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* iATU Unroll-specific register definitions
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* From 4.80 core version the address translation will be made by unroll.
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* The registers are offset from atu_base
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*/
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#define PCIE_ATU_UNR_REGION_CTRL1 0x00
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#define PCIE_ATU_UNR_REGION_CTRL2 0x04
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#define PCIE_ATU_UNR_LOWER_BASE 0x08
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#define PCIE_ATU_UNR_UPPER_BASE 0x0c
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#define PCIE_ATU_UNR_LIMIT 0x10
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#define PCIE_ATU_UNR_LOWER_TARGET 0x14
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#define PCIE_ATU_UNR_UPPER_TARGET 0x18
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#define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
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#define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
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#define PCIE_ATU_TYPE_MEM (0x0 << 0)
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#define PCIE_ATU_TYPE_IO (0x2 << 0)
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#define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
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#define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
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#define PCIE_ATU_ENABLE (0x1 << 31)
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#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
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#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
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#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
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#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
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/* Register address builder */
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#define PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(region) \
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((0x3 << 20) | ((region) << 9))
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#define PCIE_GET_ATU_INB_UNR_REG_OFFSET(region) \
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((0x3 << 20) | ((region) << 9) | (0x1 << 8))
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/* Parameters for the waiting for iATU enabled routine */
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#define LINK_WAIT_MAX_IATU_RETRIES 5
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#define LINK_WAIT_IATU 10000
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#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
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#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
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#define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */
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#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
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#define PCI_PRIMARY_BUS 0x18 /* Primary bus number */
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#define PCI_COMMAND 0x04 /* 16 bits */
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#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
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#define PCI_COMMAND_SERR 0x100 /* Enable SERR */
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#define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
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#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
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#define PCI_CLASS_BRIDGE_PCI 0x0604
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#define PCI_CLASS_DEVICE 0x0a /* Device class */
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/* 3.0 PHY Register for RK3588 */
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#define PHP_GRF_PCIESEL_CON 0x100
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#define RK3588_PCIE3PHY_GRF_CMN_CON0 0x0
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#define RK3588_PCIE3PHY_GRF_PHY0_STATUS1 0x904
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#define RK3588_PCIE3PHY_GRF_PHY1_STATUS1 0xa04
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#define RK3588_SRAM_INIT_DONE(reg) (reg & BIT(0))
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#define PHY_MODE_PCIE_AGGREGATION 4 /* PCIe3x4 */
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#endif
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