/** @file
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*
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* Copyright (c) 2022, Rockchips Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-2-Clause-Patent
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*
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**/
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#include "PcieInit.h"
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#include <Library/UefiBootServicesTableLib.h>
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#include <Library/PcdLib.h>
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#include <Library/OemMiscLib.h>
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#include <Library/PlatformPciLib.h>
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#include <Library/IoLib.h>
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#include <stdlib.h>
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#include <string.h>
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#include <malloc.h>
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#include <Library/MemoryAllocationLib.h>
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#include <stdio.h>
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#include <Library/PcdLib.h>
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#include <Library/RockchipPlatfromLib.h>
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extern VOID PcieRegWrite(UINT32 Port, UINTN Offset, UINT32 Value);
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extern EFI_STATUS PciePortReset(UINT32 HostBridgeNum, UINT32 Port);
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static UINTN rk_pcie_read(UINTN addr, UINTN size, UINT32 *val)
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{
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if ((UINTN)addr & (size - 1)) {
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*val = 0;
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return PCIBIOS_UNSUPPORTED;
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}
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if (size == 4) {
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*val = MmioRead32(addr);
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} else if (size == 2) {
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*val = MmioRead16(addr);
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} else if (size == 1) {
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*val = MmioRead8(addr);
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} else {
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*val = 0;
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return PCIBIOS_NODEV;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static UINTN rk_pcie_write(UINTN addr, UINTN size, UINT32 val)
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{
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if ((UINTN)addr & (size - 1))
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return PCIBIOS_UNSUPPORTED;
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if (size == 4)
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MmioWrite32(addr, val);
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else if (size == 2)
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MmioWrite16(addr, val);
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else if (size == 1)
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MmioWrite8(addr, val);
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else
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return PCIBIOS_NODEV;
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return PCIBIOS_SUCCESSFUL;
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}
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static UINTN __rk_pcie_read_apb(struct rk_pcie *rk_pcie, UINTN base,
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UINT32 reg, UINTN size)
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{
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int ret;
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UINT32 val;
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ret = rk_pcie_read(base + reg, size, &val);
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if (ret)
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DEBUG((EFI_D_ERROR, "Read APB address failed\n"));
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return val;
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}
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static void __rk_pcie_write_apb(struct rk_pcie *rk_pcie, UINTN base,
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UINT32 reg, UINTN size, UINT32 val)
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{
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int ret;
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ret = rk_pcie_write(base + reg, size, val);
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if (ret)
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DEBUG((EFI_D_ERROR, "Write APB address failed\n"));
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}
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static inline UINT32 rk_pcie_readl_apb(struct rk_pcie *rk_pcie, UINT32 reg)
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{
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return __rk_pcie_read_apb(rk_pcie, rk_pcie->apb_base, reg, 0x4);
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}
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static inline void rk_pcie_writel_apb(struct rk_pcie *rk_pcie, UINT32 reg,
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UINT32 val)
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{
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__rk_pcie_write_apb(rk_pcie, rk_pcie->apb_base, reg, 0x4, val);
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}
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static int rk_pcie_get_link_speed(struct rk_pcie *rk_pcie)
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{
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return (MmioRead32(rk_pcie->dbi_base + PCIE_LINK_STATUS_REG) &
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PCIE_LINK_STATUS_SPEED_MASK) >> PCIE_LINK_STATUS_SPEED_OFF;
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}
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static int rk_pcie_get_link_width(struct rk_pcie *rk_pcie)
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{
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return (MmioRead32(rk_pcie->dbi_base + PCIE_LINK_STATUS_REG) &
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PCIE_LINK_STATUS_WIDTH_MASK) >> PCIE_LINK_STATUS_WIDTH_OFF;
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}
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static inline void rk_pcie_dbi_write_enable(struct rk_pcie *rk_pcie, BOOLEAN en)
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{
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UINT32 val;
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val = MmioRead32(rk_pcie->dbi_base + PCIE_MISC_CONTROL_1_OFF);
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if (en)
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val |= PCIE_DBI_RO_WR_EN;
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else
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val &= ~PCIE_DBI_RO_WR_EN;
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MmioWrite32(rk_pcie->dbi_base + PCIE_MISC_CONTROL_1_OFF, val);
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}
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static void rk_pcie_setup_host(struct rk_pcie *rk_pcie)
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{
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UINT32 val;
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rk_pcie_dbi_write_enable(rk_pcie, TRUE);
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/* setup RC BARs */
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MmioWrite32(rk_pcie->dbi_base + PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_MEM_TYPE_64);
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MmioWrite32(rk_pcie->dbi_base + PCI_BASE_ADDRESS_1, 0x0);
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/* setup interrupt pins */
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val = MmioRead32(rk_pcie->dbi_base + PCI_INTERRUPT_LINE);
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val &= 0xffff00ff;
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val |= 0x00000100;
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//val |= 0x00000000;
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MmioWrite32(rk_pcie->dbi_base + PCI_INTERRUPT_LINE,val);
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/* setup bus numbers */
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val = MmioRead32(rk_pcie->dbi_base + PCI_PRIMARY_BUS);
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val &= 0xff000000;
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val |= 0x00ff0100;
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MmioWrite32(rk_pcie->dbi_base + PCI_PRIMARY_BUS, val);
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/* setup command register */
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val = MmioRead32(rk_pcie->dbi_base + PCI_COMMAND);
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val &= 0xffff0000;
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val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
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PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
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MmioWrite32(rk_pcie->dbi_base + PCI_COMMAND, val);
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/* program correct class for RC */
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MmioWrite16(rk_pcie->dbi_base + PCI_CLASS_DEVICE, PCI_CLASS_BRIDGE_PCI);
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//test hACK
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MmioWrite16(rk_pcie->dbi_base + PCI_CLASS_DEVICE, 0x0600);
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/* Better disable write permission right after the update */
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val = MmioRead32(rk_pcie->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
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val |= PORT_LOGIC_SPEED_CHANGE;
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MmioWrite32(rk_pcie->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL, val);
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rk_pcie_dbi_write_enable(rk_pcie, FALSE);
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}
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static void rk_pcie_configure(struct rk_pcie *pci, UINT32 cap_speed)
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{
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UINT32 val;
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rk_pcie_dbi_write_enable(pci, TRUE);
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val = MmioRead32(pci->dbi_base + PCIE_LINK_CAPABILITY);
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val &= ~TARGET_LINK_SPEED_MASK;
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val |= cap_speed;
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MmioWrite32(pci->dbi_base + PCIE_LINK_CAPABILITY, val);
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val = MmioRead32(pci->dbi_base + PCIE_LINK_CTL_2);
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val &= ~TARGET_LINK_SPEED_MASK;
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val |= cap_speed;
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MmioWrite32(pci->dbi_base + PCIE_LINK_CTL_2, val);
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rk_pcie_dbi_write_enable(pci, FALSE);
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}
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static void rk_pcie_enable_debug(struct rk_pcie *rk_pcie)
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{
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#if RK_PCIE_DBG
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rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_PTN_HIT_D0, PCIE_CLIENT_DBG_TRANSITION_DATA);
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rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_PTN_HIT_D1, PCIE_CLIENT_DBG_TRANSITION_DATA);
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rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_TRN_HIT_D0, PCIE_CLIENT_DBG_TRANSITION_DATA);
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rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_TRN_HIT_D1, PCIE_CLIENT_DBG_TRANSITION_DATA);
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rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_MODE_CON, PCIE_CLIENT_DBF_EN);
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#endif
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}
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static void rk_pcie_debug_dump(struct rk_pcie *rk_pcie)
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{
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#if RK_PCIE_DBG
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UINT32 loop;
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DEBUG((EFI_D_ERROR, "ltssm = 0x%x\n", rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_LTSSM_STATUS)));
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for (loop = 0; loop < 64; loop++)
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DEBUG((EFI_D_ERROR, "fifo_status = 0x%x\n", rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_STATUS)));
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#endif
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}
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static inline void rk_pcie_link_status_clear(struct rk_pcie *rk_pcie)
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{
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rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_GENERAL_DEBUG, 0x0);
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}
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static inline void rk_pcie_disable_ltssm(struct rk_pcie *rk_pcie)
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{
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rk_pcie_writel_apb(rk_pcie, 0x0, 0xc0008);
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}
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static inline void rk_pcie_enable_ltssm(struct rk_pcie *rk_pcie)
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{
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rk_pcie_writel_apb(rk_pcie, 0x0, 0xc000c);
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}
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static int is_link_up(struct rk_pcie *priv)
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{
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UINT32 val;
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val = rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS);
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if ((val & (RDLH_LINKUP | SMLH_LINKUP)) == 0x30000)
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return 1;
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return 0;
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}
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static int rk_pcie_link_up(struct rk_pcie *priv, UINT32 cap_speed)
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{
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int retries;
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if (is_link_up(priv)) {
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DEBUG((EFI_D_ERROR, "PCI Link already up before configuration!\n"));
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return 1;
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}
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/* DW pre link configurations */
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rk_pcie_configure(priv, cap_speed);
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/* Release the device */
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Pcie30PeReset(FALSE);
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rk_pcie_disable_ltssm(priv);
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rk_pcie_link_status_clear(priv);
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rk_pcie_enable_debug(priv);
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/* Enable LTSSM */
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rk_pcie_enable_ltssm(priv);
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for (retries = 0; retries < 500; retries++) {
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if (is_link_up(priv)) {
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DEBUG((EFI_D_ERROR, "PCIe Link up, LTSSM is 0x%x\n", rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS)));
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rk_pcie_debug_dump(priv);
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/* Link maybe in Gen switch recovery but we need to wait more 1s */
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msleep(1000);
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return 0;
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}
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DEBUG((EFI_D_ERROR, "PCIe Linking... LTSSM is 0x%x\n", rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS)));
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rk_pcie_debug_dump(priv);
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msleep(1000);
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}
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DEBUG((EFI_D_ERROR, "PCIe-%d Link Fail\n", 0));
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return -22;
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}
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static int rockchip_pcie_init_port(struct rk_pcie *priv)
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{
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int ret;
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UINT32 val;
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/* RK3588 EVB1 PCIe3L4*/
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Pcie30IoInit();
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/* Rest the device */
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Pcie30PeReset(TRUE);
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/* Set power and maybe external ref clk input */
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Pcie30PowerEn();
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msleep(100000);
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//DEBUG((EFI_D_ERROR, "0xFD5F8070 = 0x%x, 0xFEC4000c = 0x%x, 0xFEC50004 = 0x%x\n", 0));
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/* Disable power domain */
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MmioWrite32(0xFD8D8150, 0x1 << 23 | 0x1 << 21); //PD_PCIE & PD_PHP
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/* FixMe init 3.0 PHY */
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/* Phy mode: Aggregation NBNB */
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MmioWrite32(0xfd5b8000 + RK3588_PCIE3PHY_GRF_CMN_CON0, (0x7 << 16) | PHY_MODE_PCIE_AGGREGATION);
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/* 开控制器和phy时钟,撤销复位 */
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MmioWrite32(0xFD7C0A80, 0xffff0000); //CRU_SOFTRST_CON32
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MmioWrite32(0xFD7C0A84, 0xffff0000); //CRU_SOFTRST_CON33
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MmioWrite32(0xFD7C0A88, 0xffff0000); //CRU_SOFTRST_CON34
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MmioWrite32(0xFD7C0880, 0xffff0000); //CRU_GATE_CON32
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MmioWrite32(0xFD7C0884, 0xffff0000); //CRU_GATE_CON33
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MmioWrite32(0xFD7C0888, 0xffff0000); //CRU_GATE_CON34
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MmioWrite32(0xFD7C0898, 0xffff0000); //CRU_GATE_CON38
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MmioWrite32(0xFD7C089c, 0xffff0000); //CRU_GATE_CON39
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MmioWrite32(0xFD7C8A00, (0x1 << 24)); //PHPTOPCRU_SOFTRST_CON00
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MmioWrite32(0xFD7C8800, 0xffff0000); //PHPTOPCRU_GATE_CON00
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/* PHY复位 */
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MmioWrite32(0xFD7C8A00, (0x1 << 10) | (0x1 << 26));
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msleep(10);
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/* Deassert PCIe PMA output clamp mode */
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MmioWrite32(0xfd5b8000 + RK3588_PCIE3PHY_GRF_CMN_CON0, (0x1 << 8) | (0x1 << 24));
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/* 撤销PHY复位 */
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MmioWrite32(0xFD7C8A00, (0x1 << 26));
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/* 配置PHY: 3.0 PHY不用配置 */
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/* LTSSM EN ctrl mode */
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val = rk_pcie_readl_apb(priv, PCIE_CLIENT_HOT_RESET_CTRL);
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val |= PCIE_LTSSM_ENABLE_ENHANCE | (PCIE_LTSSM_ENABLE_ENHANCE << 16);
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rk_pcie_writel_apb(priv, PCIE_CLIENT_HOT_RESET_CTRL, val);
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/* Set RC mode */
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rk_pcie_dbi_write_enable(priv, TRUE);
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rk_pcie_writel_apb(priv, 0x0, 0xf00000);
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MmioWrite32(0xf50002ec, 0xfffff0);
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MmioWrite32(0xf50002f0, 0x13c0); //BAR0 resize 512G
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//io -4 0xa400008bc 0x77f41
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rk_pcie_writel_apb(priv, 0x0, 0xf00040);
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rk_pcie_setup_host(priv);
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ret = rk_pcie_link_up(priv, priv->gen);
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if (ret < 0)
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return ret;
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DEBUG((EFI_D_ERROR, "PCIe Init sucessfully (Gen%d-x%d, Bus%d)\n",
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rk_pcie_get_link_speed(priv),rk_pcie_get_link_width(priv)));
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rk_pcie_dbi_write_enable(priv, TRUE);
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msleep(10000);
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return 0;
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}
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EFI_STATUS
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PcieInitEntry (
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IN EFI_HANDLE ImageHandle,
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IN EFI_SYSTEM_TABLE *SystemTable
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)
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{
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EFI_STATUS Status = EFI_SUCCESS;
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struct rk_pcie *priv;
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int ret;
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priv = (struct rk_pcie *)AllocatePool (sizeof (struct rk_pcie));
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if (priv == NULL) {
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DEBUG((EFI_D_ERROR, "Failed to allocate priv memory!\n"));
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return EFI_OUT_OF_RESOURCES;
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}
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memset(priv, 0, sizeof(struct rk_pcie));
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/* 先调试3L4，配置Gen 3 */
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priv->gen = 3;
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priv->lane = 4;
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priv->dbi_base = PcdGet64(PcdPcieRootPortDbiBaseAddress);
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priv->apb_base = PcdGet64(PcdPcieRootPortApbBaseAddress);
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priv->cfg_base = PcdGet64(PcdPcieRootPortCfgBaseAddress);
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DEBUG((EFI_D_ERROR, "dbi_base = 0x%lx apb_base = 0x%lx cfg_base = 0x%lx\n",
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priv->dbi_base, priv->apb_base, priv->cfg_base));
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ret = rockchip_pcie_init_port(priv);
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if (ret < 0)
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return EFI_NO_MEDIA;
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return Status;
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}
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