/** @file
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This file contains the definination for host controller
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register operation routines.
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Copyright (c) 2013-2015 Intel Corporation.
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _OHCI_REG_H
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#define _OHCI_REG_H
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#define HC_STATE_RESET 0x0
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#define HC_STATE_RESUME 0x1
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#define HC_STATE_OPERATIONAL 0x2
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#define HC_STATE_SUSPEND 0x3
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#define PERIODIC_ENABLE 0x01
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#define ISOCHRONOUS_ENABLE 0x02
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#define CONTROL_ENABLE 0x04
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#define BULK_ENABLE 0x08
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#define CONTROL_BULK_RATIO 0x10
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#define HC_FUNCTIONAL_STATE 0x20
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#define INTERRUPT_ROUTING 0x40
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#define HC_RESET 0x01
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#define CONTROL_LIST_FILLED 0x02
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#define BULK_LIST_FILLED 0x04
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#define CHANGE_OWNER_REQUEST 0x08
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#define SCHEDULE_OVERRUN_COUNT 0x10
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#define SCHEDULE_OVERRUN 0x00001
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#define WRITEBACK_DONE_HEAD 0x00002
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#define START_OF_FRAME 0x00004
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#define RESUME_DETECT 0x00008
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#define UNRECOVERABLE_ERROR 0x00010
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#define FRAME_NUMBER_OVERFLOW 0x00020
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#define ROOTHUB_STATUS_CHANGE 0x00040
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#define OWNERSHIP_CHANGE 0x00080
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#define MASTER_INTERRUPT 0x00400
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#define CONTROL_HEAD 0x001
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#define BULK_HEAD 0x002
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#define DONE_HEAD 0x004
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#define Hc_HCCA 0x001
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#define Hc_PERIODIC_CURRENT 0x002
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#define Hc_CONTOL_HEAD 0x004
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#define Hc_CONTROL_CURRENT_PTR 0x008
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#define Hc_BULK_HEAD 0x010
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#define Hc_BULK_CURRENT_PTR 0x020
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#define Hc_DONE_HEAD 0x040
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#define FRAME_INTERVAL 0x008
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#define FS_LARGEST_DATA_PACKET 0x010
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#define FRMINT_TOGGLE 0x020
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#define FRAME_REMAINING 0x040
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#define FRAME_REMAIN_TOGGLE 0x080
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#define RH_DESC_A 0x00001
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#define RH_DESC_B 0x00002
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#define RH_NUM_DS_PORTS 0x00004
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#define RH_NO_PSWITCH 0x00008
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#define RH_PSWITCH_MODE 0x00010
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#define RH_DEVICE_TYPE 0x00020
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#define RH_OC_PROT_MODE 0x00040
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#define RH_NOC_PROT 0x00080
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#define RH_POTPGT 0x00100
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#define RH_NO_POTPGT 0x00200
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#define RH_DEV_REMOVABLE 0x00400
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#define RH_PORT_PWR_CTRL_MASK 0x00800
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#define RH_LOCAL_PSTAT 0x00001
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#define RH_OC_ID 0x00002
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#define RH_REMOTE_WK_ENABLE 0x00004
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#define RH_LOCAL_PSTAT_CHANGE 0x00008
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#define RH_OC_ID_CHANGE 0x00010
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#define RH_CLR_RMT_WK_ENABLE 0x00020
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#define RH_CLEAR_PORT_ENABLE 0x0001
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#define RH_SET_PORT_ENABLE 0x0002
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#define RH_SET_PORT_SUSPEND 0x0004
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#define RH_CLEAR_SUSPEND_STATUS 0x0008
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#define RH_SET_PORT_RESET 0x0010
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#define RH_SET_PORT_POWER 0x0020
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#define RH_CLEAR_PORT_POWER 0x0040
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#define RH_CONNECT_STATUS_CHANGE 0x10000
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#define RH_PORT_ENABLE_STAT_CHANGE 0x20000
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#define RH_PORT_SUSPEND_STAT_CHANGE 0x40000
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#define RH_OC_INDICATOR_CHANGE 0x80000
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#define RH_PORT_RESET_STAT_CHANGE 0x100000
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#define RH_CURR_CONNECT_STAT 0x0001
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#define RH_PORT_ENABLE_STAT 0x0002
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#define RH_PORT_SUSPEND_STAT 0x0004
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#define RH_PORT_OC_INDICATOR 0x0008
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#define RH_PORT_RESET_STAT 0x0010
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#define RH_PORT_POWER_STAT 0x0020
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#define RH_LSDEVICE_ATTACHED 0x0040
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#define RESET_SYSTEM_BUS (1 << 0)
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#define RESET_HOST_CONTROLLER (1 << 1)
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#define RESET_CLOCK_GENERATION (1 << 2)
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#define RESET_SSE_GLOBAL (1 << 5)
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#define RESET_PSPL (1 << 6)
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#define RESET_PCPL (1 << 7)
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#define RESET_SSEP1 (1 << 9)
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#define RESET_SSEP2 (1 << 10)
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#define RESET_SSEP3 (1 << 11)
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#define ONE_SECOND 1000000
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#define ONE_MILLI_SEC 1000
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#define MAX_BYTES_PER_TD 0x1000
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#define MAX_RETRY_TIMES 100
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#define PORT_NUMBER_ON_MAINSTONE2 1
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//
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// Operational Register Offsets
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//
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//
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// Command & Status Registers Offsets
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//
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#define HC_REVISION 0x00
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#define HC_CONTROL 0x04
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#define HC_COMMAND_STATUS 0x08
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#define HC_INTERRUPT_STATUS 0x0C
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#define HC_INTERRUPT_ENABLE 0x10
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#define HC_INTERRUPT_DISABLE 0x14
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//
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// Memory Pointer Offsets
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//
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#define HC_HCCA 0x18
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#define HC_PERIODIC_CURRENT 0x1C
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#define HC_CONTROL_HEAD 0x20
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#define HC_CONTROL_CURRENT_PTR 0x24
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#define HC_BULK_HEAD 0x28
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#define HC_BULK_CURRENT_PTR 0x2C
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#define HC_DONE_HEAD 0x30
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//
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// Frame Register Offsets
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//
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#define HC_FRM_INTERVAL 0x34
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#define HC_FRM_REMAINING 0x38
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#define HC_FRM_NUMBER 0x3C
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#define HC_PERIODIC_START 0x40
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#define HC_LS_THREASHOLD 0x44
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//
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// Root Hub Register Offsets
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//
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#define HC_RH_DESC_A 0x48
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#define HC_RH_DESC_B 0x4C
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#define HC_RH_STATUS 0x50
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#define HC_RH_PORT_STATUS 0x54
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#define USBHOST_OFFSET_UHCHR 0x64 // Usb Host reset register
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#define OHC_BAR_INDEX 0
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//
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// Usb Host controller register offset
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//
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#define USBHOST_OFFSET_UHCREV 0x0 // Usb Host revision register
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#define USBHOST_OFFSET_UHCHCON 0x4 // Usb Host control register
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#define USBHOST_OFFSET_UHCCOMS 0x8 // Usb Host Command Status register
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#define USBHOST_OFFSET_UHCINTS 0xC // Usb Host Interrupt Status register
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#define USBHOST_OFFSET_UHCINTE 0x10 // Usb Host Interrupt Enable register
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#define USBHOST_OFFSET_UHCINTD 0x14 // Usb Host Interrupt Disable register
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#define USBHOST_OFFSET_UHCHCCA 0x18 // Usb Host Controller Communication Area
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#define USBHOST_OFFSET_UHCPCED 0x1C // Usb Host Period Current Endpoint Descriptor
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#define USBHOST_OFFSET_UHCCHED 0x20 // Usb Host Control Head Endpoint Descriptor
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#define USBHOST_OFFSET_UHCCCED 0x24 // Usb Host Control Current Endpoint Descriptor
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#define USBHOST_OFFSET_UHCBHED 0x28 // Usb Host Bulk Head Endpoint Descriptor
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#define USBHOST_OFFSET_UHCBCED 0x2C // Usb Host Bulk Current Endpoint Descriptor
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#define USBHOST_OFFSET_UHCDHEAD 0x30 // Usb Host Done Head register
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#define USBHOST_OFFSET_UHCFMI 0x34 // Usb Host Frame Interval register
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#define USBHOST_OFFSET_UHCFMR 0x38 // Usb Host Frame Remaining register
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#define USBHOST_OFFSET_UHCFMN 0x3C // Usb Host Frame Number register
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#define USBHOST_OFFSET_UHCPERS 0x40 // Usb Host Periodic Start register
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#define USBHOST_OFFSET_UHCLST 0x44 // Usb Host Low-Speed Threshold register
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#define USBHOST_OFFSET_UHCRHDA 0x48 // Usb Host Root Hub Descriptor A register
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#define USBHOST_OFFSET_UHCRHDB 0x4C // Usb Host Root Hub Descriptor B register
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#define USBHOST_OFFSET_UHCRHS 0x50 // Usb Host Root Hub Status register
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#define USBHOST_OFFSET_UHCRHPS1 0x54 // Usb Host Root Hub Port Status 1 register
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//
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// Usb Host controller register bit fields
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//
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#pragma pack(1)
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typedef struct {
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UINT8 ProgInterface;
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UINT8 SubClassCode;
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UINT8 BaseCode;
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} USB_CLASSC;
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typedef struct {
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UINT32 Revision:8;
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UINT32 Rsvd:24;
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} HcREVISION;
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typedef struct {
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UINT32 ControlBulkRatio:2;
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UINT32 PeriodicEnable:1;
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UINT32 IsochronousEnable:1;
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UINT32 ControlEnable:1;
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UINT32 BulkEnable:1;
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UINT32 FunctionalState:2;
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UINT32 InterruptRouting:1;
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UINT32 RemoteWakeup:1;
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UINT32 RemoteWakeupEnable:1;
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UINT32 Reserved:21;
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} HcCONTROL;
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typedef struct {
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UINT32 HcReset:1;
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UINT32 ControlListFilled:1;
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UINT32 BulkListFilled:1;
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UINT32 ChangeOwnerRequest:1;
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UINT32 Reserved1:12;
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UINT32 ScheduleOverrunCount:2;
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UINT32 Reserved:14;
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} HcCOMMAND_STATUS;
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typedef struct {
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UINT32 SchedulingOverrun:1;
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UINT32 WriteBackDone:1;
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UINT32 Sof:1;
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UINT32 ResumeDetected:1;
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UINT32 UnrecoverableError:1;
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UINT32 FrameNumOverflow:1;
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UINT32 RHStatusChange:1;
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UINT32 Reserved1:23;
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UINT32 OwnerChange:1;
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UINT32 Reserved2:1;
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} HcINTERRUPT_STATUS;
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typedef struct {
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UINT32 SchedulingOverrunInt:1;
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UINT32 WriteBackDoneInt:1;
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UINT32 SofInt:1;
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UINT32 ResumeDetectedInt:1;
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UINT32 UnrecoverableErrorInt:1;
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UINT32 FrameNumOverflowInt:1;
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UINT32 RHStatusChangeInt:1;
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UINT32 Reserved:23;
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UINT32 OwnerChangedInt:1;
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UINT32 MasterInterruptEnable:1;
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} HcINTERRUPT_CONTROL;
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typedef struct {
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UINT32 Rerserved:8;
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UINT32 Hcca:24;
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} HcHCCA;
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typedef struct {
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UINT32 Reserved:4;
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UINT32 MemoryPtr:28;
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} HcMEMORY_PTR;
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typedef struct {
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UINT32 FrameInterval:14;
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UINT32 Reserved:2;
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UINT32 FSMaxDataPacket:15;
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UINT32 FrmIntervalToggle:1;
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} HcFRM_INTERVAL;
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typedef struct {
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UINT32 FrameRemaining:14;
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UINT32 Reserved:17;
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UINT32 FrameRemainingToggle:1;
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} HcFRAME_REMAINING;
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typedef struct {
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UINT32 FrameNumber:16;
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UINT32 Reserved:16;
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} HcFRAME_NUMBER;
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typedef struct {
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UINT32 PeriodicStart:14;
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UINT32 Reserved:18;
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} HcPERIODIC_START;
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typedef struct {
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UINT32 LsThreshold:12;
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UINT32 Reserved:20;
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} HcLS_THRESHOLD;
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typedef struct {
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UINT32 NumDownStrmPorts:8;
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UINT32 PowerSwitchMode:1;
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UINT32 NoPowerSwitch:1;
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UINT32 DeviceType:1;
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UINT32 OverCurrentProtMode:1;
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UINT32 NoOverCurrentProtMode:1;
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UINT32 Reserved:11;
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UINT32 PowerOnToPowerGoodTime:8;
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} HcRH_DESC_A;
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typedef struct {
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UINT32 DeviceRemovable:16;
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UINT32 PortPowerControlMask:16;
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} HcRH_DESC_B;
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typedef struct {
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UINT32 LocalPowerStat:1;
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UINT32 OverCurrentIndicator:1;
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UINT32 Reserved1:13;
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UINT32 DevRemoteWakeupEnable:1;
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UINT32 LocalPowerStatChange:1;
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UINT32 OverCurrentIndicatorChange:1;
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UINT32 Reserved2:13;
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UINT32 ClearRemoteWakeupEnable:1;
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} HcRH_STATUS;
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typedef struct {
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UINT32 CurrentConnectStat:1;
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UINT32 EnableStat:1;
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UINT32 SuspendStat:1;
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UINT32 OCIndicator:1;
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UINT32 ResetStat:1;
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UINT32 Reserved1:3;
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UINT32 PowerStat:1;
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UINT32 LsDeviceAttached:1;
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UINT32 Reserved2:6;
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UINT32 ConnectStatChange:1;
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UINT32 EnableStatChange:1;
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UINT32 SuspendStatChange:1;
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UINT32 OCIndicatorChange:1;
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UINT32 ResetStatChange:1;
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UINT32 Reserved3:11;
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} HcRHPORT_STATUS;
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typedef struct {
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UINT32 FSBIR:1;
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UINT32 FHR:1;
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UINT32 CGR:1;
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UINT32 SSDC:1;
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UINT32 UIT:1;
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UINT32 SSE:1;
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UINT32 PSPL:1;
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UINT32 PCPL:1;
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UINT32 Reserved0:1;
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UINT32 SSEP1:1;
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UINT32 SSEP2:1;
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UINT32 SSEP3:1;
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UINT32 Reserved1:20;
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} HcRESET;
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#pragma pack()
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//
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// Func List
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//
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/**
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Get OHCI operational reg value
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@param PciIo PciIo protocol instance
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@param Offset Offset of the operational reg
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@retval Value of the register
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**/
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UINT32
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OhciGetOperationalReg (
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IN USB_OHCI_HC_DEV *Ohc,
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IN UINT32 Offset
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);
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/**
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Set OHCI operational reg value
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@param PciIo PCI Bus Io protocol instance
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@param Offset Offset of the operational reg
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@param Value Value to set
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@retval EFI_SUCCESS Value set to the reg
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**/
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EFI_STATUS
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OhciSetOperationalReg (
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IN USB_OHCI_HC_DEV *Ohc,
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IN UINT32 Offset,
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IN UINT32 Value
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);
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/**
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Get HcRevision reg value
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@param PciIo PCI Bus Io protocol instance
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@retval Value of the register
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**/
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UINT32
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OhciGetHcRevision (
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IN USB_OHCI_HC_DEV *Ohc
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);
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/**
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Set HcReset reg value
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@param Ohc UHC private data
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@param Field Field to set
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@param Value Value to set
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@retval EFI_SUCCESS Value set
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**/
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EFI_STATUS
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OhciSetHcReset (
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IN USB_OHCI_HC_DEV *Ohc,
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IN UINT32 Field,
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IN UINT32 Value
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);
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/**
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Get specific field of HcReset reg value
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@param Ohc UHC private data
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@param Field Field to get
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@retval Value of the field
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**/
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UINT32
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OhciGetHcReset (
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IN USB_OHCI_HC_DEV *Ohc,
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IN UINT32 Field
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);
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/**
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Set HcControl reg value
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@param Ohc UHC private data
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@param Field Field to set
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@param Value Value to set
|
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@retval EFI_SUCCESS Value set
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**/
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EFI_STATUS
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OhciSetHcControl (
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IN USB_OHCI_HC_DEV *Ohc,
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IN UINTN Field,
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IN UINT32 Value
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);
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/**
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Get specific field of HcControl reg value
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@param Ohc UHC private data
|
@param Field Field to get
|
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@retval Value of the field
|
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**/
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|
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UINT32
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OhciGetHcControl (
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IN USB_OHCI_HC_DEV *Ohc,
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IN UINTN Field
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);
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/**
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Set HcCommand reg value
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@param Ohc UHC private data
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@param Field Field to set
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@param Value Value to set
|
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@retval EFI_SUCCESS Value set
|
|
**/
|
|
EFI_STATUS
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OhciSetHcCommandStatus (
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IN USB_OHCI_HC_DEV *Ohc,
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IN UINTN Field,
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IN UINT32 Value
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);
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/**
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Get specific field of HcCommand reg value
|
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@param Ohc UHC private data
|
@param Field Field to get
|
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@retval Value of the field
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**/
|
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UINT32
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OhciGetHcCommandStatus (
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IN USB_OHCI_HC_DEV *Ohc,
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IN UINTN Field
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);
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/**
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Clear specific fields of Interrupt Status
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@param Ohc UHC private data
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@param Field Field to clear
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@retval EFI_SUCCESS Fields cleared
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**/
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EFI_STATUS
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OhciClearInterruptStatus (
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IN USB_OHCI_HC_DEV *Ohc,
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IN UINTN Field
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);
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/**
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Get fields of HcInterrupt reg value
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@param Ohc UHC private data
|
@param Field Field to get
|
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@retval Value of the field
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**/
|
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UINT32
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OhciGetHcInterruptStatus (
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IN USB_OHCI_HC_DEV *Ohc,
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IN UINTN Field
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);
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/**
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Set Interrupt Control reg value
|
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@param Ohc UHC private data
|
@param StatEnable Enable or Disable
|
@param Field Field to set
|
@param Value Value to set
|
|
@retval EFI_SUCCESS Value set
|
|
**/
|
|
EFI_STATUS
|
OhciSetInterruptControl (
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IN USB_OHCI_HC_DEV *Ohc,
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IN BOOLEAN StatEnable,
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IN UINTN Field,
|
IN UINT32 Value
|
);
|
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/**
|
|
Get field of HcInterruptControl reg value
|
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@param Ohc UHC private data
|
@param Field Field to get
|
|
@retval Value of the field
|
|
**/
|
|
UINT32
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OhciGetHcInterruptControl (
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IN USB_OHCI_HC_DEV *Ohc,
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IN UINTN Field
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);
|
|
|
/**
|
|
Set memory pointer of specific type
|
|
@param Ohc UHC private data
|
@param PointerType Type of the pointer to set
|
@param Value Value to set
|
|
@retval EFI_SUCCESS Memory pointer set
|
|
**/
|
|
EFI_STATUS
|
OhciSetMemoryPointer(
|
IN USB_OHCI_HC_DEV *Ohc,
|
IN UINT32 PointerType,
|
IN VOID *Value
|
);
|
|
/**
|
|
Get memory pointer of specific type
|
|
@param Ohc UHC private data
|
@param PointerType Type of pointer
|
|
@retval Memory pointer of the specific type
|
|
**/
|
|
VOID *
|
OhciGetMemoryPointer (
|
IN USB_OHCI_HC_DEV *Ohc,
|
IN UINT32 PointerType
|
);
|
|
/**
|
|
Set Frame Interval value
|
|
@param Ohc UHC private data
|
@param Field Field to set
|
@param Value Value to set
|
|
@retval EFI_SUCCESS Value set
|
|
**/
|
|
EFI_STATUS
|
OhciSetFrameInterval (
|
IN USB_OHCI_HC_DEV *Ohc,
|
IN UINTN Field,
|
IN UINT32 Value
|
);
|
|
|
/**
|
|
Get field of frame interval reg value
|
|
@param Ohc UHC private data
|
@param Field Field to get
|
|
@retval Value of the field
|
|
**/
|
|
UINT32
|
OhciGetFrameInterval (
|
IN USB_OHCI_HC_DEV *Ohc,
|
IN UINTN Field
|
);
|
|
|
/**
|
|
Set Frame Remaining reg value
|
|
@param Ohc UHC private data
|
@param Value Value to set
|
|
@retval EFI_SUCCESS Value set
|
|
**/
|
|
EFI_STATUS
|
OhciSetFrameRemaining (
|
IN USB_OHCI_HC_DEV *Ohc,
|
IN UINT32 Value
|
);
|
|
/**
|
|
Get value of frame remaining reg
|
|
@param Ohc UHC private data
|
@param Field Field to get
|
|
@retval Value of frame remaining reg
|
|
**/
|
UINT32
|
OhciGetFrameRemaining (
|
IN USB_OHCI_HC_DEV *Ohc,
|
IN UINTN Field
|
);
|
|
/**
|
|
Set frame number reg value
|
|
@param Ohc UHC private data
|
@param Value Value to set
|
|
@retval EFI_SUCCESS Value set
|
|
**/
|
|
EFI_STATUS
|
OhciSetFrameNumber(
|
IN USB_OHCI_HC_DEV *Ohc,
|
IN UINT32 Value
|
);
|
|
/**
|
|
Get frame number reg value
|
|
@param Ohc UHC private data
|
|
@retval Value of frame number reg
|
|
**/
|
|
UINT32
|
OhciGetFrameNumber (
|
IN USB_OHCI_HC_DEV *Ohc
|
);
|
|
|
/**
|
|
Set period start reg value
|
|
@param Ohc UHC private data
|
@param Value Value to set
|
|
@retval EFI_SUCCESS Value set
|
|
**/
|
|
EFI_STATUS
|
OhciSetPeriodicStart (
|
IN USB_OHCI_HC_DEV *Ohc,
|
IN UINT32 Value
|
);
|
|
|
/**
|
|
Get periodic start reg value
|
|
@param Ohc UHC private data
|
|
@param Value of periodic start reg
|
|
**/
|
|
UINT32
|
OhciGetPeriodicStart (
|
IN USB_OHCI_HC_DEV *Ohc
|
);
|
|
|
/**
|
|
Set Ls Threshold reg value
|
|
@param Ohc UHC private data
|
@param Value Value to set
|
|
@retval EFI_SUCCESS Value set
|
|
**/
|
|
EFI_STATUS
|
OhciSetLsThreshold (
|
IN USB_OHCI_HC_DEV *Ohc,
|
IN UINT32 Value
|
);
|
|
/**
|
|
Get Ls Threshold reg value
|
|
@param Ohc UHC private data
|
|
@retval Value of Ls Threshold reg
|
|
**/
|
|
UINT32
|
OhciGetLsThreshold (
|
IN USB_OHCI_HC_DEV *Ohc
|
);
|
|
/**
|
|
Set Root Hub Descriptor reg value
|
|
@param Ohc UHC private data
|
@param Field Field to set
|
@param Value Value to set
|
|
@retval EFI_SUCCESS Value set
|
|
**/
|
EFI_STATUS
|
OhciSetRootHubDescriptor (
|
IN USB_OHCI_HC_DEV *Ohc,
|
IN UINTN Field,
|
IN UINT32 Value
|
);
|
|
|
/**
|
|
Get Root Hub Descriptor reg value
|
|
@param Ohc UHC private data
|
@param Field Field to get
|
|
@retval Value of the field
|
|
**/
|
|
UINT32
|
OhciGetRootHubDescriptor (
|
IN USB_OHCI_HC_DEV *Ohc,
|
IN UINTN Field
|
);
|
|
/**
|
|
Set Root Hub Status reg value
|
|
@param Ohc UHC private data
|
@param Field Field to set
|
|
@retval EFI_SUCCESS Value set
|
|
**/
|
|
EFI_STATUS
|
OhciSetRootHubStatus (
|
IN USB_OHCI_HC_DEV *Ohc,
|
IN UINTN Field
|
);
|
|
|
/**
|
|
Get Root Hub Status reg value
|
|
@param Ohc UHC private data
|
@param Field Field to get
|
|
@retval Value of the field
|
|
**/
|
|
UINT32
|
OhciGetRootHubStatus (
|
IN USB_OHCI_HC_DEV *Ohc,
|
IN UINTN Field
|
);
|
|
|
/**
|
|
Set Root Hub Port Status reg value
|
|
@param Ohc UHC private data
|
@param Index Index of the port
|
@param Field Field to set
|
|
@retval EFI_SUCCESS Value set
|
|
**/
|
|
EFI_STATUS
|
OhciSetRootHubPortStatus (
|
IN USB_OHCI_HC_DEV *Ohc,
|
IN UINT32 Index,
|
IN UINTN Field
|
);
|
|
|
/**
|
|
Get Root Hub Port Status reg value
|
|
@param Ohc UHC private data
|
@param Index Index of the port
|
@param Field Field to get
|
|
@retval Value of the field and index
|
|
**/
|
|
UINT32
|
OhciReadRootHubPortStatus (
|
IN USB_OHCI_HC_DEV *Ohc,
|
IN UINT32 Index,
|
IN UINTN Field
|
);
|
|
#endif
|
