/** @file
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RISC-V CPU library definitions.
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Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef RISCV_CPU_LIB_H_
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#define RISCV_CPU_LIB_H_
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#include "RiscVImpl.h"
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/**
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RISCV_TRAP_HANDLER
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**/
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typedef
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VOID
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(EFIAPI *RISCV_TRAP_HANDLER)(
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VOID
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);
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VOID
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RiscVSetMachineScratch (RISCV_MACHINE_MODE_CONTEXT *RiscvContext);
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UINT32
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RiscVGetMachineScratch (VOID);
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UINT32
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RiscVGetMachineTrapCause (VOID);
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UINT64
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RiscVReadMachineTimer (VOID);
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VOID
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RiscVSetMachineTimerCmp (UINT64);
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UINT64
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RiscVReadMachineTimerCmp(VOID);
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UINT64
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RiscVReadMachineInterruptEnable(VOID);
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UINT64
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RiscVReadMachineInterruptPending(VOID);
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UINT64
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RiscVReadMachineStatus(VOID);
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VOID
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RiscVWriteMachineStatus(UINT64);
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UINT64
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RiscVReadMachineTrapVector(VOID);
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UINT64
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RiscVReadMachineIsa (VOID);
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UINT64
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RiscVReadMachineVendorId (VOID);
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UINT64
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RiscVReadMachineArchitectureId (VOID);
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UINT64
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RiscVReadMachineImplementId (VOID);
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VOID
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RiscVSetSupervisorAddressTranslationRegister(UINT64);
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#endif
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