/** @file
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RISC-V package definitions.
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Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef RISCV_INDUSTRY_STANDARD_H_
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#define RISCV_INDUSTRY_STANDARD_H_
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#if defined (MDE_CPU_RISCV64)
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#define RISC_V_XLEN_BITS 64
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#else
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#endif
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#define RISC_V_ISA_ATOMIC_EXTENSION (0x00000001 << 0)
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#define RISC_V_ISA_BIT_OPERATION_EXTENSION (0x00000001 << 1)
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#define RISC_V_ISA_COMPRESSED_EXTENSION (0x00000001 << 2)
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#define RISC_V_ISA_DOUBLE_PRECISION_FP_EXTENSION (0x00000001 << 3)
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#define RISC_V_ISA_RV32E_ISA (0x00000001 << 4)
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#define RISC_V_ISA_SINGLE_PRECISION_FP_EXTENSION (0x00000001 << 5)
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#define RISC_V_ISA_ADDITIONAL_STANDARD_EXTENSION (0x00000001 << 6)
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#define RISC_V_ISA_RESERVED_1 (0x00000001 << 7)
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#define RISC_V_ISA_INTEGER_ISA_EXTENSION (0x00000001 << 8)
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#define RISC_V_ISA_DYNAMICALLY_TRANSLATED_LANGUAGE_EXTENSION (0x00000001 << 9)
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#define RISC_V_ISA_RESERVED_2 (0x00000001 << 10)
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#define RISC_V_ISA_DECIMAL_FP_EXTENSION (0x00000001 << 11)
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#define RISC_V_ISA_INTEGER_MUL_DIV_EXTENSION (0x00000001 << 12)
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#define RISC_V_ISA_USER_LEVEL_INTERRUPT_SUPPORTED (0x00000001 << 13)
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#define RISC_V_ISA_RESERVED_3 (0x00000001 << 14)
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#define RISC_V_ISA_PACKED_SIMD_EXTENSION (0x00000001 << 15)
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#define RISC_V_ISA_QUAD_PRECISION_FP_EXTENSION (0x00000001 << 16)
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#define RISC_V_ISA_RESERVED_4 (0x00000001 << 17)
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#define RISC_V_ISA_SUPERVISOR_MODE_IMPLEMENTED (0x00000001 << 18)
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#define RISC_V_ISA_TRANSATIONAL_MEMORY_EXTENSION (0x00000001 << 19)
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#define RISC_V_ISA_USER_MODE_IMPLEMENTED (0x00000001 << 20)
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#define RISC_V_ISA_VECTOR_EXTENSION (0x00000001 << 21)
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#define RISC_V_ISA_RESERVED_5 (0x00000001 << 22)
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#define RISC_V_ISA_NON_STANDARD_EXTENSION (0x00000001 << 23)
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#define RISC_V_ISA_RESERVED_6 (0x00000001 << 24)
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#define RISC_V_ISA_RESERVED_7 (0x00000001 << 25)
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//
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// RISC-V CSR definitions.
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//
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//
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// Machine information
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//
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#define RISCV_CSR_MACHINE_MVENDORID 0xF11
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#define RISCV_CSR_MACHINE_MARCHID 0xF12
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#define RISCV_CSR_MACHINE_MIMPID 0xF13
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#define RISCV_CSR_MACHINE_HARRID 0xF14
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//
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// Machine Trap Setup.
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//
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#define RISCV_CSR_MACHINE_MSTATUS 0x300
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#define RISCV_CSR_MACHINE_MISA 0x301
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#define RISCV_CSR_MACHINE_MEDELEG 0x302
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#define RISCV_CSR_MACHINE_MIDELEG 0x303
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#define RISCV_CSR_MACHINE_MIE 0x304
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#define RISCV_CSR_MACHINE_MTVEC 0x305
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#define RISCV_TIMER_COMPARE_BITS 32
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//
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// Machine Timer and Counter.
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//
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//#define RISCV_CSR_MACHINE_MTIME 0x701
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//#define RISCV_CSR_MACHINE_MTIMEH 0x741
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//
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// Machine Trap Handling.
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//
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#define RISCV_CSR_MACHINE_MSCRATCH 0x340
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#define RISCV_CSR_MACHINE_MEPC 0x341
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#define RISCV_CSR_MACHINE_MCAUSE 0x342
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#define MACHINE_MCAUSE_EXCEPTION_ MASK 0x0f
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#define MACHINE_MCAUSE_INTERRUPT (RISC_V_XLEN_BITS - 1)
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#define RISCV_CSR_MACHINE_MBADADDR 0x343
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#define RISCV_CSR_MACHINE_MIP 0x344
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//
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// Machine Protection and Translation.
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//
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#define RISCV_CSR_MACHINE_MBASE 0x380
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#define RISCV_CSR_MACHINE_MBOUND 0x381
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#define RISCV_CSR_MACHINE_MIBASE 0x382
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#define RISCV_CSR_MACHINE_MIBOUND 0x383
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#define RISCV_CSR_MACHINE_MDBASE 0x384
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#define RISCV_CSR_MACHINE_MDBOUND 0x385
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//
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// Supervisor mode CSR.
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//
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#define RISCV_CSR_SUPERVISOR_SSTATUS 0x100
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#define SSTATUS_SIE_BIT_POSITION 1
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#define SSTATUS_SPP_BIT_POSITION 8
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#define RISCV_CSR_SUPERVISOR_SIE 0x104
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#define RISCV_CSR_SUPERVISOR_SSCRATCH 0x140
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#define RISCV_CSR_SUPERVISOR_SEPC 0x141
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#define RISCV_CSR_SUPERVISOR_SCAUSE 0x142
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#define SCAUSE_USER_SOFTWARE_INT 0
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#define SCAUSE_SUPERVISOR_SOFTWARE_INT 1
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#define SCAUSE_USER_TIMER_INT 4
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#define SCAUSE_SUPERVISOR_TIMER_INT 5
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#define SCAUSE_USER_EXTERNAL_INT 8
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#define SCAUSE_SUPERVISOR_EXTERNAL_INT 9
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#define RISCV_CSR_SUPERVISOR_STVAL 0x143
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#define RISCV_CSR_SUPERVISOR_SIP 0x144
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#define RISCV_CSR_SUPERVISOR_SATP 0x180
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#if defined (MDE_CPU_RISCV64)
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#define RISCV_SATP_MODE_MASK 0xF000000000000000
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#define RISCV_SATP_MODE_BIT_POSITION 60
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#endif
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#define RISCV_SATP_MODE_OFF 0
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#define RISCV_SATP_MODE_SV32 1
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#define RISCV_SATP_MODE_SV39 8
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#define RISCV_SATP_MODE_SV48 9
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#define RISCV_SATP_MODE_SV57 10
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#define RISCV_SATP_MODE_SV64 11
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#define SATP64_ASID_MASK 0x0FFFF00000000000
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#define SATP64_PPN_MASK 0x00000FFFFFFFFFFF
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#define RISCV_CAUSE_MISALIGNED_FETCH 0x0
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#define RISCV_CAUSE_FETCH_ACCESS 0x1
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#define RISCV_CAUSE_ILLEGAL_INSTRUCTION 0x2
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#define RISCV_CAUSE_BREAKPOINT 0x3
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#define RISCV_CAUSE_MISALIGNED_LOAD 0x4
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#define RISCV_CAUSE_LOAD_ACCESS 0x5
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#define RISCV_CAUSE_MISALIGNED_STORE 0x6
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#define RISCV_CAUSE_STORE_ACCESS 0x7
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#define RISCV_CAUSE_USER_ECALL 0x8
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#define RISCV_CAUSE_HYPERVISOR_ECALL 0x9
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#define RISCV_CAUSE_SUPERVISOR_ECALL 0xa
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#define RISCV_CAUSE_MACHINE_ECALL 0xb
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#define RISCV_CAUSE_FETCH_PAGE_FAULT 0xc
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#define RISCV_CAUSE_LOAD_PAGE_FAULT 0xd
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#define RISCV_CAUSE_STORE_PAGE_FAULT 0xf
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#define RISCV_CAUSE_FETCH_GUEST_PAGE_FAULT 0x14
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#define RISCV_CAUSE_LOAD_GUEST_PAGE_FAULT 0x15
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#define RISCV_CAUSE_STORE_GUEST_PAGE_FAULT 0x17
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//
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// Machine Read-Write Shadow of Hypervisor Read-Only Registers
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//
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#define RISCV_CSR_HTIMEW 0xB01
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#define RISCV_CSR_HTIMEHW 0xB81
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//
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// Machine Host-Target Interface (Non-Standard Berkeley Extension)
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//
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#define RISCV_CSR_MTOHOST 0x780
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#define RISCV_CSR_MFROMHOST 0x781
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#endif
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