/** @file
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I2c Lib to control I2c controller.
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Copyright 2020 NXP
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef I2C_LIB_INTERNAL_H__
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#define I2C_LIB_INTERNAL_H__
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#include <Pi/PiI2c.h>
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#include <Uefi.h>
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/** Module Disable
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0b - The module is enabled. You must clear this field before any other IBCR
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fields have any effect.
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1b - The module is reset and disabled. This is the power-on reset situation.
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When high, the interface is held in reset, but registers can still be
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accessed. Status register fields (IBSR) are not valid when the module
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is disabled.
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**/
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#define I2C_IBCR_MDIS BIT7
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// I2c Bus Interrupt Enable
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#define I2C_IBCR_IBIE BIT6
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/** Master / Slave Mode 0b - Slave mode 1b - Master mode
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When you change this field from 0 to 1, the module generates a START signal
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on the bus and selects the master mode. When you change this field from 1 to
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0, the module generates a STOP signal and changes the operation mode from
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master to slave. You should generate a STOP signal only if IBSR[IBIF]=1.
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The module clears this field without generating a STOP signal when the
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master loses arbitration.
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*/
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#define I2C_IBCR_MSSL BIT5
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// 0b - Receive 1b - Transmit
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#define I2C_IBCR_TXRX BIT4
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/** Data acknowledge disable
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Values written to this field are only used when the I2C module is a receiver,
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not a transmitter.
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0b - The module sends an acknowledge signal to the bus at the 9th clock bit
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after receiving one byte of data.
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1b - The module does not send an acknowledge-signal response (that is,
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acknowledge bit = 1).
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**/
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#define I2C_IBCR_NOACK BIT3
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/**Repeat START
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If the I2C module is the current bus master, and you program RSTA=1, the I2C
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module generates a repeated START condition. This field always reads as a 0.
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If you attempt a repeated START at the wrong time, if the bus is owned by
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another master the result is loss of arbitration.
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**/
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#define I2C_IBCR_RSTA BIT2
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// DMA enable
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#define I2C_IBCR_DMAEN BIT1
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// Transfer Complete
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#define I2C_IBSR_TCF BIT7
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// I2C bus Busy. 0b - Bus is idle, 1b - Bus is busy
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#define I2C_IBSR_IBB BIT5
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// Arbitration Lost. software must clear this field by writing a one to it.
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#define I2C_IBSR_IBAL BIT4
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// I2C bus interrupt flag
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#define I2C_IBSR_IBIF BIT1
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// Received acknowledge 0b - Acknowledge received 1b - No acknowledge received
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#define I2C_IBSR_RXAK BIT0
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//Bus idle interrupt enable
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#define I2C_IBIC_BIIE BIT7
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// Glitch filter enable
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#define I2C_IBDBG_GLFLT_EN BIT3
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#define I2C_BUS_TEST_BUSY TRUE
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#define I2C_BUS_TEST_IDLE !I2C_BUS_TEST_BUSY
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#define I2C_BUS_TEST_RX_ACK TRUE
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#define I2C_BUS_NO_TEST_RX_ACK !I2C_BUS_TEST_RX_ACK
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#define ARRAY_LAST_ELEM(x) (x)[ARRAY_SIZE (x) - 1]
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#define I2C_NUM_RETRIES 500
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typedef struct _I2C_REGS {
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UINT8 Ibad; // I2c Bus Address Register
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UINT8 Ibfd; // I2c Bus Frequency Divider Register
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UINT8 Ibcr; // I2c Bus Control Register
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UINT8 Ibsr; // I2c Bus Status Register
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UINT8 Ibdr; // I2C Bus Data I/O Register
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UINT8 Ibic; // I2C Bus Interrupt Config Register
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UINT8 Ibdbg; // I2C Bus Debug Register
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} I2C_REGS;
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/*
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* sorted list of clock divisor, Ibfd register value pairs
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*/
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typedef struct _I2C_CLOCK_DIVISOR_PAIR {
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UINT16 Divisor;
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UINT8 Ibfd; // I2c Bus Frequency Divider Register value
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} I2C_CLOCK_DIVISOR_PAIR;
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typedef struct {
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UINTN OperationCount;
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EFI_I2C_OPERATION Operation[2];
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} I2C_REG_REQUEST;
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#endif // I2C_LIB_INTERNAL_H__
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