/** @file
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I2c Lib to control I2c controller.
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Copyright 2017, 2020 NXP
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SPDX-License-Identifier: BSD-2-Clause-Patent
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@par Revision Reference:
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- PI Version 1.7
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@par Glossary:
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- Ibfd - I2c Bus Frequency Divider
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**/
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#include <Uefi.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/I2cLib.h>
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#include <Library/IoLib.h>
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#include <Library/TimerLib.h>
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#include "I2cLibInternal.h"
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/**
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I2C divisor and Ibfd register values when glitch filter is enabled
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In case of duplicate SCL Divisor value, the Ibfd value with high MUL value
|
has been selected. A higher MUL value results in a lower sampling rate of
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the I2C signals. This gives the I2C module greater immunity against glitches
|
in the I2C signals.
|
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These values can be referred from NXP QorIQ Layerscape series SOC Reference
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Manual in which this I2C ip has been used. e.g. LX2160ARM, LS1043ARM
|
**/
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STATIC CONST I2C_CLOCK_DIVISOR_PAIR mI2cClockDivisorGlitchEnabled[] = {
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{ 34, 0x0 }, { 36, 0x1 }, { 38, 0x2 }, { 40, 0x3 },
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{ 42, 0x4 }, { 44, 0x8 }, { 48, 0x9 }, { 52, 0xA },
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{ 54, 0x7 }, { 56, 0xB }, { 60, 0xC }, { 64, 0x10 },
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{ 68, 0x40 }, { 72, 0x41 }, { 76, 0x42 }, { 80, 0x43 },
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{ 84, 0x44 }, { 88, 0x48 }, { 96, 0x49 }, { 104, 0x4A },
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{ 108, 0x47 }, { 112, 0x4B }, { 120, 0x4C }, { 128, 0x50 },
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{ 136, 0x80 }, { 144, 0x81 }, { 152, 0x82 }, { 160, 0x83 },
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{ 168, 0x84 }, { 176, 0x88 }, { 192, 0x89 }, { 208, 0x8A },
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{ 216, 0x87 }, { 224, 0x8B }, { 240, 0x8C }, { 256, 0x90 },
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{ 288, 0x91 }, { 320, 0x92 }, { 336, 0x8F }, { 352, 0x93 },
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{ 384, 0x98 }, { 416, 0x95 }, { 448, 0x99 }, { 480, 0x96 },
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{ 512, 0x9A }, { 576, 0x9B }, { 640, 0xA0 }, { 704, 0x9D },
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{ 768, 0xA1 }, { 832, 0x9E }, { 896, 0xA2 }, { 960, 0x67 },
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{ 1024, 0xA3 }, { 1152, 0xA4 }, { 1280, 0xA8 }, { 1536, 0xA9 },
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{ 1792, 0xAA }, { 1920, 0xA7 }, { 2048, 0xAB }, { 2304, 0xAC },
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{ 2560, 0xB0 }, { 3072, 0xB1 }, { 3584, 0xB2 }, { 3840, 0xAF },
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{ 4096, 0xB3 }, { 4608, 0xB4 }, { 5120, 0xB8 }, { 6144, 0xB9 },
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{ 7168, 0xBA }, { 7680, 0xB7 }, { 8192, 0xBB }, { 9216, 0xBC },
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{ 10240, 0xBD }, { 12288, 0xBE }, { 15360, 0xBF }
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};
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/**
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I2C divisor and Ibfd register values when glitch filter is disabled
|
|
In case of duplicate SCL Divisor value, the Ibfd value with high MUL value
|
has been selected. A higher MUL value results in a lower sampling rate of
|
the I2C signals. This gives the I2C module greater immunity against glitches
|
in the I2C signals.
|
|
These values can be referred from NXP QorIQ Layerscape series SOC Reference
|
Manual in which this I2C ip has been used. e.g. LX2160ARM, LS1043ARM
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**/
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STATIC CONST I2C_CLOCK_DIVISOR_PAIR mI2cClockDivisorGlitchDisabled[] = {
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{ 20, 0x0 },{ 22, 0x1 },{ 24, 0x2 },{ 26, 0x3 },
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{ 28, 0x8 },{ 30, 0x5 },{ 32, 0x9 },{ 34, 0x6 },
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{ 36, 0x0A },{ 40, 0x40 },{ 44, 0x41 },{ 48, 0x42 },
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{ 52, 0x43 },{ 56, 0x48 },{ 60, 0x45 },{ 64, 0x49 },
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{ 68, 0x46 },{ 72, 0x4A },{ 80, 0x80 },{ 88, 0x81 },
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{ 96, 0x82 },{ 104, 0x83 },{ 112, 0x88 },{ 120, 0x85 },
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{ 128, 0x89 },{ 136, 0x86 },{ 144, 0x8A },{ 160, 0x8B },
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{ 176, 0x8C },{ 192, 0x90 },{ 208, 0x56 },{ 224, 0x91 },
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{ 240, 0x1F },{ 256, 0x92 },{ 272, 0x8F },{ 288, 0x93 },
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{ 320, 0x98 },{ 352, 0x95 },{ 384, 0x99 },{ 416, 0x96 },
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{ 448, 0x9A },{ 480, 0x5F },{ 512, 0x9B },{ 576, 0x9C },
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{ 640, 0xA0 },{ 768, 0xA1 },{ 896, 0xA2 },{ 960, 0x9F },
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{ 1024, 0xA3 },{ 1152, 0xA4 },{ 1280, 0xA8 },{ 1536, 0xA9 },
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{ 1792, 0xAA },{ 1920, 0xA7 },{ 2048, 0xAB },{ 2304, 0xAC },
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{ 2560, 0xAD },{ 3072, 0xB1 },{ 3584, 0xB2 },{ 3840, 0xAF },
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{ 4096, 0xB3 },{ 4608, 0xB4 },{ 5120, 0xB8 },{ 6144, 0xB9 },
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{ 7168, 0xBA },{ 7680, 0xB7 },{ 8192, 0xBB },{ 9216, 0xBC },
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{ 10240, 0xBD },{ 12288, 0xBE },{ 15360, 0xBF }
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};
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/**
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A-009203 : I2C may not work reliably with the default setting
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Description : The clocking circuitry of I2C module may not work reliably due
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to the slow rise time of SCL signal.
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Workaround : Enable the receiver digital filter by setting IBDBG[GLFLT_EN]
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to 1. refer https://patchwork.ozlabs.org/patch/453575/
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**/
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STATIC
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VOID
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I2cErratumA009203 (
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IN UINTN Base
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)
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{
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I2C_REGS *Regs;
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Regs = (I2C_REGS *)Base;
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MmioOr8 ((UINTN)&Regs->Ibdbg, I2C_IBDBG_GLFLT_EN);
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}
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/**
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software reset of the entire I2C module.
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The module is reset and disabled.
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Status register fields (IBSR) are cleared.
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@param[in] Base Base Address of I2c controller's registers
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@return EFI_SUCCESS successfuly reset the I2c module
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**/
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EFI_STATUS
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I2cReset (
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IN UINTN Base
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)
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{
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I2C_REGS *Regs;
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Regs = (I2C_REGS *)Base;
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MmioOr8 ((UINTN)&Regs->Ibcr, I2C_IBCR_MDIS);
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MmioOr8 ((UINTN)&Regs->Ibsr, (I2C_IBSR_IBAL | I2C_IBSR_IBIF));
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MmioAnd8 ((UINTN)&Regs->Ibcr, ~(I2C_IBCR_IBIE | I2C_IBCR_DMAEN));
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MmioAnd8 ((UINTN)&Regs->Ibic, (UINT8)(~I2C_IBIC_BIIE));
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return EFI_SUCCESS;
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}
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/**
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Configure I2c bus to operate at a given speed
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@param[in] Base Base Address of I2c controller's registers
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@param[in] I2cBusClock Input clock to I2c controller
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@param[in] Speed speed to be configured for I2c bus
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@return EFI_SUCCESS successfuly setup the i2c bus
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**/
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EFI_STATUS
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I2cInitialize (
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IN UINTN Base,
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IN UINT64 I2cBusClock,
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IN UINT64 Speed
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)
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{
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I2C_REGS *Regs;
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UINT16 ClockDivisor;
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UINT8 Ibfd; // I2c Bus Frequency Divider Register
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CONST I2C_CLOCK_DIVISOR_PAIR *ClockDivisorPair;
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UINT32 ClockDivisorPairSize;
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UINT32 Index;
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Regs = (I2C_REGS *)Base;
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if (FeaturePcdGet (PcdI2cErratumA009203)) {
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// Apply Erratum A-009203 before writing Ibfd register
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I2cErratumA009203 (Base);
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}
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Ibfd = 0;
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ClockDivisor = (I2cBusClock + Speed - 1) / Speed;
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if (MmioRead8 ((UINTN)&Regs->Ibdbg) & I2C_IBDBG_GLFLT_EN) {
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ClockDivisorPair = mI2cClockDivisorGlitchEnabled;
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ClockDivisorPairSize = ARRAY_SIZE (mI2cClockDivisorGlitchEnabled);
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} else {
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ClockDivisorPair = mI2cClockDivisorGlitchDisabled;
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ClockDivisorPairSize = ARRAY_SIZE (mI2cClockDivisorGlitchDisabled);
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}
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if (ClockDivisor > ClockDivisorPair[ClockDivisorPairSize - 1].Divisor) {
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Ibfd = ClockDivisorPair[ClockDivisorPairSize - 1].Ibfd;
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} else {
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for (Index = 0; Index < ClockDivisorPairSize; Index++) {
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if (ClockDivisorPair[Index].Divisor >= ClockDivisor) {
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Ibfd = ClockDivisorPair[Index].Ibfd;
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break;
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}
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}
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}
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MmioWrite8 ((UINTN)&Regs->Ibfd, Ibfd);
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I2cReset (Base);
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return EFI_SUCCESS;
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}
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STATIC
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EFI_STATUS
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I2cBusTestBusBusy (
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IN I2C_REGS *Regs,
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IN BOOLEAN TestBusy
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)
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{
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UINT32 Index;
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UINT8 Reg;
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for (Index = 0; Index < I2C_NUM_RETRIES; Index++) {
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Reg = MmioRead8 ((UINTN)&Regs->Ibsr);
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if (Reg & I2C_IBSR_IBAL) {
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MmioWrite8 ((UINTN)&Regs->Ibsr, Reg);
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return EFI_NOT_READY;
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}
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if (TestBusy && (Reg & I2C_IBSR_IBB)) {
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break;
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}
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if (!TestBusy && !(Reg & I2C_IBSR_IBB)) {
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break;
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}
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MicroSecondDelay (1);
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}
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if (Index == I2C_NUM_RETRIES) {
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return EFI_TIMEOUT;
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}
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return EFI_SUCCESS;
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}
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STATIC
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EFI_STATUS
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I2cTransferComplete (
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IN I2C_REGS *Regs,
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IN BOOLEAN TestRxAck
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)
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{
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UINT32 Index;
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UINT8 Reg;
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for (Index = 0; Index < I2C_NUM_RETRIES; Index++) {
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Reg = MmioRead8 ((UINTN)&Regs->Ibsr);
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if (Reg & I2C_IBSR_IBIF) {
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// Write 1 to clear the IBIF field
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MmioWrite8 ((UINTN)&Regs->Ibsr, Reg);
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break;
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}
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MicroSecondDelay (1);
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}
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if (Index == I2C_NUM_RETRIES) {
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return EFI_TIMEOUT;
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}
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if (TestRxAck && (Reg & I2C_IBSR_RXAK)) {
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return EFI_NO_RESPONSE;
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}
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if (Reg & I2C_IBSR_TCF) {
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return EFI_SUCCESS;
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}
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return EFI_DEVICE_ERROR;
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}
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STATIC
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EFI_STATUS
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I2cRead (
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IN I2C_REGS *Regs,
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IN UINT32 SlaveAddress,
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IN EFI_I2C_OPERATION *Operation,
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IN BOOLEAN IsLastOperation
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)
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{
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EFI_STATUS Status;
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UINTN Index;
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// Write Slave Address
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MmioWrite8 ((UINTN)&Regs->Ibdr, (SlaveAddress << BIT0) | BIT0);
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Status = I2cTransferComplete (Regs, I2C_BUS_TEST_RX_ACK);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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// select Receive mode.
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MmioAnd8 ((UINTN)&Regs->Ibcr, ~I2C_IBCR_TXRX);
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if (Operation->LengthInBytes > 1) {
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// Set No ACK = 0
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MmioAnd8 ((UINTN)&Regs->Ibcr, ~I2C_IBCR_NOACK);
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}
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// Perform a dummy read to initiate the receive operation.
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MmioRead8 ((UINTN)&Regs->Ibdr);
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for (Index = 0; Index < Operation->LengthInBytes; Index++) {
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Status = I2cTransferComplete (Regs, I2C_BUS_NO_TEST_RX_ACK);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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if (Index == (Operation->LengthInBytes - 2)) {
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// Set No ACK = 1
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MmioOr8 ((UINTN)&Regs->Ibcr, I2C_IBCR_NOACK);
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} else if (Index == (Operation->LengthInBytes - 1)) {
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if (!IsLastOperation) {
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// select Transmit mode (for repeat start)
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MmioOr8 ((UINTN)&Regs->Ibcr, I2C_IBCR_TXRX);
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} else {
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// Generate Stop Signal
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MmioAnd8 ((UINTN)&Regs->Ibcr, ~(I2C_IBCR_MSSL | I2C_IBCR_TXRX));
|
Status = I2cBusTestBusBusy (Regs, I2C_BUS_TEST_IDLE);
|
if (EFI_ERROR (Status)) {
|
return Status;
|
}
|
}
|
}
|
Operation->Buffer[Index] = MmioRead8 ((UINTN)&Regs->Ibdr);
|
}
|
|
return EFI_SUCCESS;
|
}
|
|
STATIC
|
EFI_STATUS
|
I2cWrite (
|
IN I2C_REGS *Regs,
|
IN UINT32 SlaveAddress,
|
IN EFI_I2C_OPERATION *Operation
|
)
|
{
|
EFI_STATUS Status;
|
UINTN Index;
|
|
// Write Slave Address
|
MmioWrite8 ((UINTN)&Regs->Ibdr, (SlaveAddress << BIT0) & (UINT8)(~BIT0));
|
Status = I2cTransferComplete (Regs, I2C_BUS_TEST_RX_ACK);
|
if (EFI_ERROR (Status)) {
|
return Status;
|
}
|
|
// Write Data
|
for (Index = 0; Index < Operation->LengthInBytes; Index++) {
|
MmioWrite8 ((UINTN)&Regs->Ibdr, Operation->Buffer[Index]);
|
Status = I2cTransferComplete (Regs, I2C_BUS_TEST_RX_ACK);
|
if (EFI_ERROR (Status)) {
|
return Status;
|
}
|
}
|
return EFI_SUCCESS;
|
}
|
|
STATIC
|
EFI_STATUS
|
I2cStop (
|
IN I2C_REGS *Regs
|
)
|
{
|
EFI_STATUS Status;
|
UINT8 Reg;
|
|
Status = EFI_SUCCESS;
|
Reg = MmioRead8 ((UINTN)&Regs->Ibsr);
|
if (Reg & I2C_IBSR_IBB) {
|
// Generate Stop Signal
|
MmioAnd8 ((UINTN)&Regs->Ibcr, ~(I2C_IBCR_MSSL | I2C_IBCR_TXRX));
|
Status = I2cBusTestBusBusy (Regs, I2C_BUS_TEST_IDLE);
|
if (EFI_ERROR (Status)) {
|
return Status;
|
}
|
}
|
|
// Disable I2c Controller
|
MmioOr8 ((UINTN)&Regs->Ibcr, I2C_IBCR_MDIS);
|
|
return Status;
|
}
|
|
STATIC
|
EFI_STATUS
|
I2cStart (
|
IN I2C_REGS *Regs
|
)
|
{
|
EFI_STATUS Status;
|
|
MmioOr8 ((UINTN)&Regs->Ibsr, (I2C_IBSR_IBAL | I2C_IBSR_IBIF));
|
MmioAnd8 ((UINTN)&Regs->Ibcr, (UINT8)(~I2C_IBCR_MDIS));
|
|
//Wait controller to be stable
|
MicroSecondDelay (1);
|
|
// Generate Start Signal
|
MmioOr8 ((UINTN)&Regs->Ibcr, I2C_IBCR_MSSL);
|
Status = I2cBusTestBusBusy (Regs, I2C_BUS_TEST_BUSY);
|
if (EFI_ERROR (Status)) {
|
return Status;
|
}
|
|
// Select Transmit Mode. set No ACK = 1
|
MmioOr8 ((UINTN)&Regs->Ibcr, (I2C_IBCR_TXRX | I2C_IBCR_NOACK));
|
|
return Status;
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}
|
|
/**
|
Transfer data to/from I2c slave device
|
|
@param[in] Base Base Address of I2c controller's registers
|
@param[in] SlaveAddress Slave Address from which data is to be read
|
@param[in] RequestPacket Pointer to an EFI_I2C_REQUEST_PACKET structure
|
describing the I2C transaction
|
|
@return EFI_SUCCESS successfuly transfer the data
|
@return EFI_DEVICE_ERROR There was an error while transferring data through
|
I2c bus
|
@return EFI_NO_RESPONSE There was no Ack from i2c device
|
@return EFI_TIMEOUT I2c Bus is busy
|
@return EFI_NOT_READY I2c Bus Arbitration lost
|
**/
|
EFI_STATUS
|
I2cBusXfer (
|
IN UINTN Base,
|
IN UINT32 SlaveAddress,
|
IN EFI_I2C_REQUEST_PACKET *RequestPacket
|
)
|
{
|
UINTN Index;
|
I2C_REGS *Regs;
|
EFI_I2C_OPERATION *Operation;
|
EFI_STATUS Status;
|
BOOLEAN IsLastOperation;
|
|
Regs = (I2C_REGS *)Base;
|
IsLastOperation = FALSE;
|
|
Status = I2cBusTestBusBusy (Regs, I2C_BUS_TEST_IDLE);
|
if (EFI_ERROR (Status)) {
|
goto ErrorExit;
|
}
|
|
Status = I2cStart (Regs);
|
if (EFI_ERROR (Status)) {
|
goto ErrorExit;
|
}
|
|
for (Index = 0, Operation = RequestPacket->Operation;
|
Index < RequestPacket->OperationCount;
|
Index++, Operation++) {
|
if (Index == (RequestPacket->OperationCount - 1)) {
|
IsLastOperation = TRUE;
|
}
|
// Send repeat start after first transmit/recieve
|
if (Index) {
|
MmioOr8 ((UINTN)&Regs->Ibcr, I2C_IBCR_RSTA);
|
Status = I2cBusTestBusBusy (Regs, I2C_BUS_TEST_BUSY);
|
if (EFI_ERROR (Status)) {
|
goto ErrorExit;
|
}
|
}
|
// Read/write data
|
if (Operation->Flags & I2C_FLAG_READ) {
|
Status = I2cRead (Regs, SlaveAddress, Operation, IsLastOperation);
|
} else {
|
Status = I2cWrite (Regs, SlaveAddress, Operation);
|
}
|
if (EFI_ERROR (Status)) {
|
goto ErrorExit;
|
}
|
}
|
|
ErrorExit:
|
|
I2cStop (Regs);
|
|
return Status;
|
}
|
|
/**
|
Read a register from I2c slave device. This API is wrapper around I2cBusXfer
|
|
@param[in] Base Base Address of I2c controller's registers
|
@param[in] SlaveAddress Slave Address from which register value is
|
to be read
|
@param[in] RegAddress Register Address in Slave's memory map
|
@param[in] RegAddressWidthInBytes Number of bytes in RegAddress to send to
|
I2c Slave for simple reads without any
|
register, make this value = 0
|
(RegAddress is don't care in that case)
|
@param[out] RegValue Value to be read from I2c slave's regiser
|
@param[in] RegValueNumBytes Number of bytes to read from I2c slave
|
register
|
|
@return EFI_SUCCESS successfuly read the registers
|
@return EFI_DEVICE_ERROR There was an error while transferring data through
|
I2c bus
|
@return EFI_NO_RESPONSE There was no Ack from i2c device
|
@return EFI_TIMEOUT I2c Bus is busy
|
@return EFI_NOT_READY I2c Bus Arbitration lost
|
**/
|
EFI_STATUS
|
I2cBusReadReg (
|
IN UINTN Base,
|
IN UINT32 SlaveAddress,
|
IN UINT64 RegAddress,
|
IN UINT8 RegAddressWidthInBytes,
|
OUT UINT8 *RegValue,
|
IN UINT32 RegValueNumBytes
|
)
|
{
|
EFI_I2C_OPERATION *Operations;
|
I2C_REG_REQUEST RequestPacket;
|
UINTN OperationCount;
|
UINT8 Address[sizeof (RegAddress)];
|
UINT8 *AddressPtr;
|
EFI_STATUS Status;
|
|
ZeroMem (&RequestPacket, sizeof (RequestPacket));
|
OperationCount = 0;
|
Operations = RequestPacket.Operation;
|
AddressPtr = Address;
|
|
if (RegAddressWidthInBytes > ARRAY_SIZE (Address)) {
|
return EFI_INVALID_PARAMETER;
|
}
|
|
if (RegAddressWidthInBytes != 0) {
|
Operations[OperationCount].LengthInBytes = RegAddressWidthInBytes;
|
Operations[OperationCount].Buffer = AddressPtr;
|
while (RegAddressWidthInBytes--) {
|
*AddressPtr++ = RegAddress >> (8 * RegAddressWidthInBytes);
|
}
|
OperationCount++;
|
}
|
|
Operations[OperationCount].LengthInBytes = RegValueNumBytes;
|
Operations[OperationCount].Buffer = RegValue;
|
Operations[OperationCount].Flags = I2C_FLAG_READ;
|
OperationCount++;
|
|
RequestPacket.OperationCount = OperationCount;
|
|
Status = I2cBusXfer (
|
Base, SlaveAddress,
|
(EFI_I2C_REQUEST_PACKET *)&RequestPacket
|
);
|
|
return Status;
|
}
|
