/** DUart.h
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* Header defining the DUART constants (Base addresses, sizes, flags)
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*
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* Based on Serial I/O Port library headers available in PL011Uart.h
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*
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* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
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* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
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* Copyright 2017, 2020 NXP
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*
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* SPDX-License-Identifier: BSD-2-Clause-Patent
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*
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**/
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#ifndef DUART_H_
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#define DUART_H_
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// FIFO Control Register
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#define DUART_FCR_FIFO_EN 0x01 /* Fifo enable */
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#define DUART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
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#define DUART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
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#define DUART_FCR_DMA_SELECT 0x08 /* For DMA applications */
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#define DUART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
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#define DUART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */
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#define DUART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */
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#define DUART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */
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#define DUART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */
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#define DUART_FCR_RXSR 0x02 /* Receiver soft reset */
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#define DUART_FCR_TXSR 0x04 /* Transmitter soft reset */
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// Modem Control Register
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#define DUART_MCR_DTR 0x01 /* Reserved */
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#define DUART_MCR_RTS 0x02 /* RTS */
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#define DUART_MCR_OUT1 0x04 /* Reserved */
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#define DUART_MCR_OUT2 0x08 /* Reserved */
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#define DUART_MCR_LOOP 0x10 /* Enable loopback test mode */
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#define DUART_MCR_AFE 0x20 /* AFE (Auto Flow Control) */
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#define DUART_MCR_DMA_EN 0x04
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#define DUART_MCR_TX_DFR 0x08
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// Line Control Register
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/*
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* Note: if the word length is 5 bits (DUART_LCR_WLEN5), then setting
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* DUART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
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*/
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#define DUART_LCR_WLS_MSK 0x03 /* character length select mask */
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#define DUART_LCR_WLS_5 0x00 /* 5 bit character length */
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#define DUART_LCR_WLS_6 0x01 /* 6 bit character length */
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#define DUART_LCR_WLS_7 0x02 /* 7 bit character length */
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#define DUART_LCR_WLS_8 0x03 /* 8 bit character length */
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#define DUART_LCR_STB 0x04 /* # stop Bits, off=1, on=1.5 or 2) */
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#define DUART_LCR_PEN 0x08 /* Parity eneble */
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#define DUART_LCR_EPS 0x10 /* Even Parity Select */
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#define DUART_LCR_STKP 0x20 /* Stick Parity */
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#define DUART_LCR_SBRK 0x40 /* Set Break */
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#define DUART_LCR_BKSE 0x80 /* Bank select enable */
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#define DUART_LCR_DLAB 0x80 /* Divisor latch access bit */
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// Line Status Register
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#define DUART_LSR_DR 0x01 /* Data ready */
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#define DUART_LSR_OE 0x02 /* Overrun */
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#define DUART_LSR_PE 0x04 /* Parity error */
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#define DUART_LSR_FE 0x08 /* Framing error */
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#define DUART_LSR_BI 0x10 /* Break */
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#define DUART_LSR_THRE 0x20 /* Xmit holding register empty */
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#define DUART_LSR_TEMT 0x40 /* Xmitter empty */
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#define DUART_LSR_ERR 0x80 /* Error */
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// Modem Status Register
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#define DUART_MSR_DCTS 0x01 /* Delta CTS */
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#define DUART_MSR_DDSR 0x02 /* Reserved */
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#define DUART_MSR_TERI 0x04 /* Reserved */
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#define DUART_MSR_DDCD 0x08 /* Reserved */
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#define DUART_MSR_CTS 0x10 /* Clear to Send */
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#define DUART_MSR_DSR 0x20 /* Reserved */
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#define DUART_MSR_RI 0x40 /* Reserved */
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#define DUART_MSR_DCD 0x80 /* Reserved */
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// Interrupt Identification Register
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#define DUART_IIR_NO_INT 0x01 /* No interrupts pending */
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#define DUART_IIR_ID 0x06 /* Mask for the interrupt ID */
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#define DUART_IIR_MSI 0x00 /* Modem status interrupt */
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#define DUART_IIR_THRI 0x02 /* Transmitter holding register empty */
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#define DUART_IIR_RDI 0x04 /* Receiver data interrupt */
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#define DUART_IIR_RLSI 0x06 /* Receiver line status interrupt */
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// Interrupt Enable Register
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#define DUART_IER_MSI 0x08 /* Enable Modem status interrupt */
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#define DUART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
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#define DUART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
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#define DUART_IER_RDI 0x01 /* Enable receiver data interrupt */
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// LCR defaults
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#define DUART_LCR_8N1 0x03
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#define DUART_LCRVAL DUART_LCR_8N1 /* 8 data, 1 stop, no parity */
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#define DUART_MCRVAL (DUART_MCR_DTR | \
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DUART_MCR_RTS) /* RTS/DTR */
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#define DUART_FCRVAL (DUART_FCR_FIFO_EN | \
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DUART_FCR_RXSR | \
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DUART_FCR_TXSR) /* Clear & enable FIFOs */
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#define URBR 0x0
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#define UTHR 0x0
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#define UDLB 0x0
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#define UDMB 0x1
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#define UIER 0x1
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#define UIIR 0x2
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#define UFCR 0x2
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#define UAFR 0x2
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#define ULCR 0x3
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#define UMCR 0x4
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#define ULSR 0x5
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#define UMSR 0x6
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#define USCR 0x7
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#define UDSR 0x10
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#endif /* DUART_H_ */
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