/** @file
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Copyright 2018-2020 NXP
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef SOC_H__
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#define SOC_H__
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#include <Chassis.h>
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/**
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Soc Memory Map
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**/
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#define LX2160A_DRAM0_PHYS_ADDRESS (BASE_2GB)
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#define LX2160A_DRAM0_SIZE (SIZE_2GB)
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#define LX2160A_DRAM1_PHYS_ADDRESS (BASE_128GB + BASE_2GB)
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#define LX2160A_DRAM1_SIZE (SIZE_128GB - SIZE_2GB) // 126 GB
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#define LX2160A_DRAM2_PHYS_ADDRESS (BASE_256GB + BASE_128GB)
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#define LX2160A_DRAM2_SIZE (SIZE_128GB)
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#define LX2160A_CCSR_PHYS_ADDRESS (BASE_16MB)
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#define LX2160A_CCSR_SIZE (SIZE_256MB - SIZE_16MB) // 240MB
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#define LX2160A_FSPI0_PHYS_ADDRESS (BASE_512MB)
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#define LX2160A_FSPI0_SIZE (SIZE_256MB)
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#define LX2160A_PCI1_PHYS_ADDRESS FixedPcdGet64 (PcdPciExp1BaseAddr)
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#define LX2160A_PCI_SIZE SIZE_32GB
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#define LX2160A_DCFG_ADDRESS NXP_LAYERSCAPE_CHASSIS3V2_DCFG_ADDRESS
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// SVR
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#define SVR_LX2160A 0x873600
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/**
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Reset Control Word (RCW) Bits
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RCWSR contains the Reset Configuration Word (RCW) information written with
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values read from flash memory by the device at power-on reset and read-only
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upon exiting reset.
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RCW bits in RCWSR registers are same as bit position in Little Endian (LE)
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RCW Bits |
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in RCWSR |
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(LSBit 0)| 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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------------------------------------------------------------------------------------------------
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LE | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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(LSBit 0)|
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Moreover the RCW bits are to be interpreted in below fasion
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Bit(s) | Field Name | Description | Notes/comments
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----------------------------------------------------------------------
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6-2 | SYS_PLL_RAT | System PLL Multiplier/Ratio | This field selects the platform
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| | | clock:SYSCLK ratio.
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| | | 0_0100 4:1
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| | | 0_0110 6:1
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| | | 0_1000 8:1
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| | | 0_1101 13:1
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| | | 0_1111 15:1
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**/
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#define SYS_PLL_RAT(x) (((x) & 0x7c) >> 2) // Bits 6-2
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typedef NXP_LAYERSCAPE_CHASSIS3V2_DEVICE_CONFIG LX2160A_DEVICE_CONFIG;
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#endif // SOC_H__
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