/** @Soc.c
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SoC specific Library containg functions to initialize various SoC components
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Copyright 2017-2020 NXP
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Base.h>
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#include <Library/ChassisLib.h>
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#include <Library/DebugLib.h>
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#include <Library/SocLib.h>
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#include <Soc.h>
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/**
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Return the input clock frequency to an IP Module.
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This function reads the RCW bits and calculates the PLL multiplier/divider
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values to be applied to various IP modules.
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If a module is disabled or doesn't exist on platform, then return zero.
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@param[in] BaseClock Base clock to which PLL multiplier/divider values is
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to be applied.
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@param[in] ClockType Variable of Type NXP_IP_CLOCK. Indicates which IP clock
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is to be retrieved.
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@param[in] Args Variable argument list which is parsed based on
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ClockType. e.g. if the ClockType is NXP_I2C_CLOCK, then
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the second argument will be interpreted as controller
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number. e.g. if there are four i2c controllers in SOC,
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then this value can be 0, 1, 2, 3
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e.g. if ClockType is NXP_CORE_CLOCK, then second
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argument is interpreted as cluster number and third
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argument is interpreted as core number (within the
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cluster)
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@return Actual Clock Frequency. Return value 0 should be
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interpreted as clock not being provided to IP.
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**/
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UINT64
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SocGetClock (
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IN UINT64 BaseClock,
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IN NXP_IP_CLOCK ClockType,
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IN VA_LIST Args
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)
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{
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LS1046A_DEVICE_CONFIG *Dcfg;
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UINT32 RcwSr;
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UINT64 ReturnValue;
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ReturnValue = 0;
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Dcfg = (LS1046A_DEVICE_CONFIG *)LS1046A_DCFG_ADDRESS;
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switch (ClockType) {
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case NXP_UART_CLOCK:
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case NXP_I2C_CLOCK:
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RcwSr = DcfgRead32 ((UINTN)&Dcfg->RcwSr[0]);
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ReturnValue = BaseClock * SYS_PLL_RAT (RcwSr);
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ReturnValue >>= 1; // 1/2 Platform Clock
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break;
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default:
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break;
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}
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return ReturnValue;
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}
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/**
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Function to select pins depending upon pcd using supplemental
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configuration unit(SCFG) extended RCW controlled pinmux control
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register which contains the bits to provide pin multiplexing control.
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This register is reset on HRESET.
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**/
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STATIC
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VOID
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ConfigScfgMux (VOID)
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{
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LS1046A_SUPPLEMENTAL_CONFIG *Scfg;
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UINT32 UsbPwrFault;
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Scfg = (LS1046A_SUPPLEMENTAL_CONFIG *)LS1046A_SCFG_ADDRESS;
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// Configures functionality of the IIC3_SCL to USB2_DRVVBUS
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// Configures functionality of the IIC3_SDA to USB2_PWRFAULT
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// USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA
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ScfgWrite32 ((UINTN)&Scfg->RcwPMuxCr0, SCFG_RCWPMUXCRO_NOT_SELCR_USB);
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ScfgWrite32 ((UINTN)&Scfg->UsbDrvVBusSelCr, SCFG_USBDRVVBUS_SELCR_USB1);
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UsbPwrFault = (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB3_SHIFT) |
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(SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB2_SHIFT) |
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(SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB1_SHIFT);
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ScfgWrite32 ((UINTN)&Scfg->UsbPwrFaultSelCr, UsbPwrFault);
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ScfgWrite32 ((UINTN)&Scfg->UsbPwrFaultSelCr, UsbPwrFault);
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}
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STATIC
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VOID
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ApplyErrata (
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VOID
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)
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{
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ErratumA008997 ();
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ErratumA009007 ();
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ErratumA009008 ();
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ErratumA009798 ();
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}
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/**
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Function to initialize SoC specific constructs
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**/
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VOID
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SocInit (
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VOID
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)
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{
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LS1046A_SUPPLEMENTAL_CONFIG *Scfg;
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Scfg = (LS1046A_SUPPLEMENTAL_CONFIG *)LS1046A_SCFG_ADDRESS;
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/* Make SEC, SATA and USB reads and writes snoopable */
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ScfgOr32((UINTN)&Scfg->SnpCnfgCr, SCFG_SNPCNFGCR_SECRDSNP |
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SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP |
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SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_USB2RDSNP |
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SCFG_SNPCNFGCR_USB2WRSNP | SCFG_SNPCNFGCR_USB3RDSNP |
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SCFG_SNPCNFGCR_USB3WRSNP | SCFG_SNPCNFGCR_SATARDSNP |
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SCFG_SNPCNFGCR_SATAWRSNP);
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ApplyErrata ();
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ChassisInit ();
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//
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// Due to the extensive functionality present on the chip and the limited number of external
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// signals available, several functional blocks share signal resources through multiplexing.
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// In this case when there is alternate functionality between multiple functional blocks,
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// the signal's function is determined at the chip level (rather than at the block level)
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// typically by a reset configuration word (RCW) option. Some of the signals' function are
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// determined externel to RCW at Power-on Reset Sequence.
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//
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ConfigScfgMux ();
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return;
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}
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