/** @file
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Copyright 2020 NXP
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef SOC_H__
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#define SOC_H__
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#include <Chassis.h>
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/**
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Soc Memory Map
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**/
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#define LS1046A_DRAM0_PHYS_ADDRESS (BASE_2GB)
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#define LS1046A_DRAM0_SIZE (SIZE_2GB)
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#define LS1046A_DRAM1_PHYS_ADDRESS (BASE_32GB + BASE_2GB)
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#define LS1046A_DRAM1_SIZE (SIZE_32GB - SIZE_2GB) // 30 GB
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#define LS1046A_CCSR_PHYS_ADDRESS (BASE_16MB)
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#define LS1046A_CCSR_SIZE (SIZE_256MB - SIZE_16MB) // 240MB
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#define LS1046A_QSPI0_PHYS_ADDRESS (BASE_1GB)
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#define LS1046A_QSPI0_SIZE (SIZE_512MB)
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#define LS1046A_DCFG_ADDRESS NXP_LAYERSCAPE_CHASSIS2_DCFG_ADDRESS
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#define LS1046A_SCFG_ADDRESS NXP_LAYERSCAPE_CHASSIS2_SCFG_ADDRESS
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/**
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Reset Control Word (RCW) Bits
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RCWSR contains the Reset Configuration Word (RCW) information written with
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values read from flash memory by the device at power-on reset and read-only
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upon exiting reset.
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RCW bits in RCWSR registers are mirror of bit position in Little Endian (LE)
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RCW Bits |
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in RCWSR |
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(MSBit 0)| 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
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------------------------------------------------------------------------------------------------
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LE | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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(LSBit 0)|
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Moreover the RCW bits are to be interpreted in below fasion
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Bit(s) | Field Name | Description | Notes/comments
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----------------------------------------------------------------------
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2-6 | SYS_PLL_RAT | System PLL Multiplier/Ratio | This field selects the platform
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| | | clock:SYSCLK ratio.
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| | | 0_0011 3:1
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| | | 0_0100 4:1
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| | | 0_1101 13:1
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| | | 0_1111 15:1
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| | | 1_0000 16:1
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which is why the RCW bits in RCWSR registers are parsed this way
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**/
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#define SYS_PLL_RAT(x) (((x) >> 25) & 0x1f) // Bits 2-6
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typedef NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG LS1046A_DEVICE_CONFIG;
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typedef NXP_LAYERSCAPE_CHASSIS2_SUPPLEMENTAL_CONFIG LS1046A_SUPPLEMENTAL_CONFIG;
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#endif // SOC_H__
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