/** @file
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Copyright 2017, 2020 NXP
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Library/BaseLib.h>
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#include <Library/DebugLib.h>
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#include <Library/IoLib.h>
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#include <Library/NonDiscoverableDeviceRegistrationLib.h>
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#include <Library/UefiBootServicesTableLib.h>
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#include "UsbHcd.h"
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STATIC
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VOID
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XhciSetBeatBurstLength (
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IN UINTN UsbReg
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)
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{
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DWC3 *Dwc3Reg;
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Dwc3Reg = (VOID *)(UsbReg + DWC3_REG_OFFSET);
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MmioAndThenOr32 ((UINTN)&Dwc3Reg->GSBusCfg0, ~USB3_ENABLE_BEAT_BURST_MASK,
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USB3_ENABLE_BEAT_BURST);
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MmioOr32 ((UINTN)&Dwc3Reg->GSBusCfg1, USB3_SET_BEAT_BURST_LIMIT);
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}
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STATIC
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VOID
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Dwc3SetFladj (
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IN DWC3 *Dwc3Reg,
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IN UINT32 Val
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)
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{
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MmioOr32 ((UINTN)&Dwc3Reg->GFLAdj, GFLADJ_30MHZ_REG_SEL |
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GFLADJ_30MHZ (Val));
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}
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STATIC
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VOID
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Dwc3SetMode (
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IN DWC3 *Dwc3Reg,
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IN UINT32 Mode
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)
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{
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MmioAndThenOr32 ((UINTN)&Dwc3Reg->GCtl,
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~(DWC3_GCTL_PRTCAPDIR (DWC3_GCTL_PRTCAP_OTG)),
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DWC3_GCTL_PRTCAPDIR (Mode));
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}
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/**
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This function issues phy reset and core soft reset
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@param Dwc3Reg Pointer to DWC3 register.
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**/
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STATIC
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VOID
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Dwc3CoreSoftReset (
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IN DWC3 *Dwc3Reg
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)
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{
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//
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// Put core in reset before resetting PHY
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//
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MmioOr32 ((UINTN)&Dwc3Reg->GCtl, DWC3_GCTL_CORESOFTRESET);
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//
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// Assert USB2 PHY reset
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//
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MmioOr32 ((UINTN)&Dwc3Reg->GUsb3PipeCtl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
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//
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// Assert USB3 PHY reset
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//
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MmioOr32 ((UINTN)&Dwc3Reg->GUsb2PhyCfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
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MemoryFence ();
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//
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// Clear USB3 PHY reset
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//
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MmioAnd32 ((UINTN)&Dwc3Reg->GUsb3PipeCtl[0], ~DWC3_GUSB3PIPECTL_PHYSOFTRST);
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//
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// Clear USB2 PHY reset
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//
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MmioAnd32 ((UINTN)&Dwc3Reg->GUsb2PhyCfg, ~DWC3_GUSB2PHYCFG_PHYSOFTRST);
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MemoryFence ();
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//
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// Take core out of reset, PHYs are stable now
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//
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MmioAnd32 ((UINTN)&Dwc3Reg->GCtl, ~DWC3_GCTL_CORESOFTRESET);
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}
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/**
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This function performs low-level initialization of DWC3 Core
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@param Dwc3Reg Pointer to DWC3 register.
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**/
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STATIC
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EFI_STATUS
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Dwc3CoreInit (
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IN DWC3 *Dwc3Reg
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)
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{
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UINT32 Revision;
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UINT32 Reg;
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UINTN Dwc3Hwparams1;
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Revision = MmioRead32 ((UINTN)&Dwc3Reg->GSnpsId);
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//
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// This should read as 0x5533, ascii of U3(DWC_usb3) followed by revision num
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//
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if ((Revision & DWC3_GSNPSID_MASK) != DWC3_SYNOPSYS_ID) {
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DEBUG ((DEBUG_ERROR,"This is not a DesignWare USB3 DRD Core.\n"));
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return EFI_NOT_FOUND;
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}
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Dwc3CoreSoftReset (Dwc3Reg);
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Reg = MmioRead32 ((UINTN)&Dwc3Reg->GCtl);
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Reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
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Reg &= ~DWC3_GCTL_DISSCRAMBLE;
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Dwc3Hwparams1 = MmioRead32 ((UINTN)&Dwc3Reg->GHwParams1);
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if (DWC3_GHWPARAMS1_EN_PWROPT (Dwc3Hwparams1) ==
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DWC3_GHWPARAMS1_EN_PWROPT_CLK) {
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Reg &= ~DWC3_GCTL_DSBLCLKGTNG;
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} else {
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DEBUG ((DEBUG_WARN,"No power optimization available.\n"));
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}
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if ((Revision & DWC3_RELEASE_MASK) < DWC3_RELEASE_190a) {
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Reg |= DWC3_GCTL_U2RSTECN;
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}
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MmioWrite32 ((UINTN)&Dwc3Reg->GCtl, Reg);
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return EFI_SUCCESS;
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}
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STATIC
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EFI_STATUS
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XhciCoreInit (
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IN UINTN UsbReg
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)
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{
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EFI_STATUS Status;
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DWC3 *Dwc3Reg;
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Dwc3Reg = (VOID *)(UsbReg + DWC3_REG_OFFSET);
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Status = Dwc3CoreInit (Dwc3Reg);
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if (EFI_ERROR (Status)) {
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DEBUG ((DEBUG_ERROR, "Dwc3CoreInit Failed for controller 0x%x (0x%r) \n",
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UsbReg, Status));
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return Status;
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}
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Dwc3SetMode (Dwc3Reg, DWC3_GCTL_PRTCAP_HOST);
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Dwc3SetFladj (Dwc3Reg, GFLADJ_30MHZ_DEFAULT);
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return Status;
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}
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NON_DISCOVERABLE_DEVICE_INIT
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EFIAPI
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InitializeUsbController (
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IN UINTN UsbReg
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)
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{
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EFI_STATUS Status;
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Status = XhciCoreInit (UsbReg);
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if (EFI_ERROR (Status)) {
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DEBUG ((DEBUG_ERROR, "USB Controller init Failed for %d (0x%r)\n",
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UsbReg, Status));
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return (VOID *)EFI_DEVICE_ERROR;
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}
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//
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// Change beat burst and outstanding pipelined transfers requests
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//
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XhciSetBeatBurstLength (UsbReg);
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return EFI_SUCCESS;
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}
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/**
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This function gets registered as a callback to perform USB controller intialization
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@param Event Event whose notification function is being invoked.
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@param Context Pointer to the notification function's context.
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**/
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VOID
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EFIAPI
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UsbEndOfDxeCallback (
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IN EFI_EVENT Event,
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IN VOID *Context
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)
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{
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EFI_STATUS Status;
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UINT32 NumUsbController;
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UINT32 ControllerAddr;
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UINT32 Index;
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gBS->CloseEvent (Event);
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NumUsbController = PcdGet32 (PcdNumUsbController);
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for (Index = 0; Index < NumUsbController; Index++) {
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ControllerAddr = PcdGet64 (PcdUsbBaseAddr) +
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(Index * PcdGet32 (PcdUsbSize));
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Status = RegisterNonDiscoverableMmioDevice (
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NonDiscoverableDeviceTypeXhci,
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NonDiscoverableDeviceDmaTypeNonCoherent,
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InitializeUsbController (ControllerAddr),
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NULL,
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1,
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ControllerAddr, PcdGet32 (PcdUsbSize)
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);
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if (EFI_ERROR (Status)) {
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DEBUG ((DEBUG_ERROR, "Failed to register USB device 0x%x, error 0x%r \n",
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ControllerAddr, Status));
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}
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}
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}
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/**
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The Entry Point of module. It follows the standard UEFI driver model.
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@param[in] ImageHandle The firmware allocated handle for the EFI image.
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@param[in] SystemTable A pointer to the EFI System Table.
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@retval EFI_SUCCESS The entry point is executed successfully.
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@retval other Some error occurs when executing this entry point.
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**/
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EFI_STATUS
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EFIAPI
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InitializeUsbHcd (
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IN EFI_HANDLE ImageHandle,
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IN EFI_SYSTEM_TABLE *SystemTable
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)
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{
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EFI_STATUS Status;
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EFI_EVENT EndOfDxeEvent;
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Status = gBS->CreateEventEx (
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EVT_NOTIFY_SIGNAL,
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TPL_CALLBACK,
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UsbEndOfDxeCallback,
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NULL,
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&gEfiEndOfDxeEventGroupGuid,
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&EndOfDxeEvent
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);
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return Status;
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}
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