/** @file
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Copyright 2020 NXP
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef CHASSIS_H__
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#define CHASSIS_H__
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#include <Uefi.h>
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#define NXP_LAYERSCAPE_CHASSIS2_DCFG_ADDRESS 0x1EE0000
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#define NXP_LAYERSCAPE_CHASSIS2_SCFG_ADDRESS 0x1570000
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#define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFFFFE)
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#define SVR_MAJOR(svr) (((svr) >> 4) & 0xf)
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#define SVR_MINOR(svr) (((svr) >> 0) & 0xf)
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/* SMMU Defintions */
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#define SMMU_BASE_ADDR 0x09000000
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#define SMMU_REG_SCR0 (SMMU_BASE_ADDR + 0x0)
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#define SMMU_REG_SACR (SMMU_BASE_ADDR + 0x10)
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#define SMMU_REG_NSCR0 (SMMU_BASE_ADDR + 0x400)
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#define SCR0_USFCFG_MASK 0x00000400
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#define SCR0_CLIENTPD_MASK 0x00000001
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#define SACR_PAGESIZE_MASK 0x00010000
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#define USB_PHY1_BASE_ADDRESS 0x084F0000
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#define USB_PHY2_BASE_ADDRESS 0x08500000
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#define USB_PHY3_BASE_ADDRESS 0x08510000
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/**
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The Device Configuration Unit provides general purpose configuration and
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status for the device. These registers only support 32-bit accesses.
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**/
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#pragma pack(1)
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typedef struct {
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UINT8 Reserved0[0x70 - 0x0];
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UINT32 DeviceDisableRegister1; // Device Disable Register 1
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UINT32 DeviceDisableRegister2; // Device Disable Register 2
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UINT32 DeviceDisableRegister3; // Device Disable Register 3
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UINT32 DeviceDisableRegister4; // Device Disable Register 4
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UINT32 DeviceDisableRegister5; // Device Disable Register 5
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UINT8 Reserved1[0xa4 - 0x84];
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UINT32 Svr; // System Version Register
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UINT8 Reserved2[0x100 - 0xa8];
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UINT32 RcwSr[16]; // Reset Control Word Status Register
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} NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG;
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#pragma pack()
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/* Supplemental Configuration Unit (SCFG) */
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typedef struct {
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UINT8 Res000[0x070-0x000];
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UINT32 Usb1Prm1Cr;
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UINT32 Usb1Prm2Cr;
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UINT32 Usb1Prm3Cr;
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UINT32 Usb2Prm1Cr;
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UINT32 Usb2Prm2Cr;
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UINT32 Usb2Prm3Cr;
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UINT32 Usb3Prm1Cr;
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UINT32 Usb3Prm2Cr;
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UINT32 Usb3Prm3Cr;
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UINT8 Res094[0x100-0x094];
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UINT32 Usb2Icid;
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UINT32 Usb3Icid;
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UINT8 Res108[0x114-0x108];
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UINT32 DmaIcid;
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UINT32 SataIcid;
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UINT32 Usb1Icid;
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UINT32 QeIcid;
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UINT32 SdhcIcid;
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UINT32 EdmaIcid;
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UINT32 EtrIcid;
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UINT32 Core0SftRst;
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UINT32 Core1SftRst;
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UINT32 Core2SftRst;
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UINT32 Core3SftRst;
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UINT8 Res140[0x158-0x140];
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UINT32 AltCBar;
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UINT32 QspiCfg;
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UINT8 Res160[0x180-0x160];
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UINT32 DmaMcr;
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UINT8 Res184[0x188-0x184];
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UINT32 GicAlign;
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UINT32 DebugIcid;
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UINT8 Res190[0x1a4-0x190];
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UINT32 SnpCnfgCr;
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#define SCFG_SNPCNFGCR_SECRDSNP BIT31
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#define SCFG_SNPCNFGCR_SECWRSNP BIT30
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#define SCFG_SNPCNFGCR_SATARDSNP BIT23
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#define SCFG_SNPCNFGCR_SATAWRSNP BIT22
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#define SCFG_SNPCNFGCR_USB1RDSNP BIT21
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#define SCFG_SNPCNFGCR_USB1WRSNP BIT20
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#define SCFG_SNPCNFGCR_USB2RDSNP BIT15
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#define SCFG_SNPCNFGCR_USB2WRSNP BIT16
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#define SCFG_SNPCNFGCR_USB3RDSNP BIT13
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#define SCFG_SNPCNFGCR_USB3WRSNP BIT14
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UINT8 Res1a8[0x1ac-0x1a8];
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UINT32 IntpCr;
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UINT8 Res1b0[0x204-0x1b0];
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UINT32 CoreSrEnCr;
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UINT8 Res208[0x220-0x208];
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UINT32 RvBar00;
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UINT32 RvBar01;
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UINT32 RvBar10;
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UINT32 RvBar11;
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UINT32 RvBar20;
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UINT32 RvBar21;
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UINT32 RvBar30;
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UINT32 RvBar31;
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UINT32 LpmCsr;
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UINT8 Res244[0x400-0x244];
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UINT32 QspIdQScr;
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UINT32 EcgTxcMcr;
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UINT32 SdhcIoVSelCr;
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UINT32 RcwPMuxCr0;
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/**Setting RCW PinMux Register bits 17-19 to select USB2_DRVVBUS
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Setting RCW PinMux Register bits 21-23 to select USB2_PWRFAULT
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Setting RCW PinMux Register bits 25-27 to select USB3_DRVVBUS
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Setting RCW PinMux Register bits 29-31 to select USB3_DRVVBUS
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**/
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#define SCFG_RCWPMUXCRO_SELCR_USB 0x3333
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/**Setting RCW PinMux Register bits 17-19 to select USB2_DRVVBUS
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Setting RCW PinMux Register bits 21-23 to select USB2_PWRFAULT
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Setting RCW PinMux Register bits 25-27 to select IIC4_SCL
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Setting RCW PinMux Register bits 29-31 to select IIC4_SDA
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**/
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#define SCFG_RCWPMUXCRO_NOT_SELCR_USB 0x3300
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UINT32 UsbDrvVBusSelCr;
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#define SCFG_USBDRVVBUS_SELCR_USB1 0x00000000
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#define SCFG_USBDRVVBUS_SELCR_USB2 0x00000001
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#define SCFG_USBDRVVBUS_SELCR_USB3 0x00000003
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UINT32 UsbPwrFaultSelCr;
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#define SCFG_USBPWRFAULT_INACTIVE 0x00000000
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#define SCFG_USBPWRFAULT_SHARED 0x00000001
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#define SCFG_USBPWRFAULT_DEDICATED 0x00000002
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#define SCFG_USBPWRFAULT_USB3_SHIFT 4
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#define SCFG_USBPWRFAULT_USB2_SHIFT 2
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#define SCFG_USBPWRFAULT_USB1_SHIFT 0
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UINT32 UsbRefclkSelcr1;
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UINT32 UsbRefclkSelcr2;
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UINT32 UsbRefclkSelcr3;
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UINT8 Res424[0x600-0x424];
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UINT32 ScratchRw[4];
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UINT8 Res610[0x680-0x610];
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UINT32 CoreBCr;
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UINT8 Res684[0x1000-0x684];
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UINT32 Pex1MsiIr;
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UINT32 Pex1MsiR;
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UINT8 Res1008[0x2000-0x1008];
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UINT32 Pex2;
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UINT32 Pex2MsiR;
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UINT8 Res2008[0x3000-0x2008];
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UINT32 Pex3MsiIr;
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UINT32 Pex3MsiR;
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} NXP_LAYERSCAPE_CHASSIS2_SUPPLEMENTAL_CONFIG;
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#endif // CHASSIS_H__
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