/**
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Copyright (c) 2019, Marvell International Ltd. and its affiliates.
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SPDX-License-Identifier: BSD-2-Clause-Patent
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Glossary - abbreviations used in Marvell SampleAtReset library implementation:
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ICU - Interrupt Consolidation Unit
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AP - Application Processor hardware block (CN913x incorporates AP807)
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CP - South Bridge hardware blocks (CN913x incorporates CP115)
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**/
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#define CP_GIC_SPI_CP0_SDMMC 64
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#define CP_GIC_SPI_PP2_CP0_PORT0 65, 68, 71, 74, 77, 90
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#define CP_GIC_SPI_PP2_CP0_PORT1 66, 69, 72, 75, 78, 89
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#define CP_GIC_SPI_PP2_CP0_PORT2 67, 70, 73, 76, 79, 88
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#define CP_GIC_SPI_CP0_EIP_RNG0 80
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#define CP_GIC_SPI_CP0_USB_H1 81
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#define CP_GIC_SPI_CP0_USB_H0 82
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#define CP_GIC_SPI_CP0_SATA_H0 83
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#define CP_GIC_SPI_CP0_UART0 84
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#define CP_GIC_SPI_CP0_UART1 85
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#define CP_GIC_SPI_CP0_UART2 86
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#define CP_GIC_SPI_CP0_UART3 87
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#define CP_GIC_SPI_CP1_SDMMC 96
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#define CP_GIC_SPI_PP2_CP1_PORT0 97, 100, 103, 106, 109, 122
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#define CP_GIC_SPI_PP2_CP1_PORT1 98, 101, 104, 107, 110, 121
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#define CP_GIC_SPI_PP2_CP1_PORT2 99, 102, 105, 108, 111, 120
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#define CP_GIC_SPI_CP1_EIP_RNG0 112
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#define CP_GIC_SPI_CP1_USB_H1 113
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#define CP_GIC_SPI_CP1_USB_H0 114
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#define CP_GIC_SPI_CP1_SATA_H0 115
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#define CP_GIC_SPI_CP1_UART0 116
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#define CP_GIC_SPI_CP1_UART1 117
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#define CP_GIC_SPI_CP1_UART2 118
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#define CP_GIC_SPI_CP1_UART3 119
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#define CP_GIC_SPI_CP2_SDMMC 288
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#define CP_GIC_SPI_PP2_CP2_PORT0 289, 292, 295, 298, 301, 314
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#define CP_GIC_SPI_PP2_CP2_PORT1 290, 293, 296, 299, 302, 313
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#define CP_GIC_SPI_PP2_CP2_PORT2 291, 294, 297, 300, 303, 312
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#define CP_GIC_SPI_CP2_EIP_RNG0 304
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#define CP_GIC_SPI_CP2_USB_H1 305
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#define CP_GIC_SPI_CP2_USB_H0 306
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#define CP_GIC_SPI_CP2_SATA_H0 307
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#define CP_GIC_SPI_CP2_UART0 308
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#define CP_GIC_SPI_CP2_UART1 309
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#define CP_GIC_SPI_CP2_UART2 310
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#define CP_GIC_SPI_CP2_UART3 311
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