/********************************************************************************
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Copyright (C) 2016 Marvell International Ltd.
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SPDX-License-Identifier: BSD-2-Clause-Patent
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*******************************************************************************/
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#include <Library/ArmLib.h>
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#include <Library/ArmPlatformLib.h>
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#include <Library/DebugLib.h>
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#include <Library/PcdLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/IoLib.h>
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#define MPP_PIN_VAL(pin,func) (((func) & 0xf) << ((pin) * 4))
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#define MPP_MAX_REGS 8
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#define MPP_PINS_PER_REG 8
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#define PCD_PINS_PER_GROUP 10
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#define SD_MMC_PHY_AP_MPP_OFFSET 0x100
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#define SD_MMC_PHY_CP0_MPP_OFFSET 0x424
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#define MPP_ON_SDPHY_ENABLE (1 << 0)
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#define MAX_CHIPS 4
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#define GET_PCD_PTR(id,num) PcdGetPtr(PcdChip##id##MppSel##num)
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#define GET_PIN_COUNT(id) PcdGet32(PcdChip##id##MppPinCount)
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#define GET_BASE(id) PcdGet64(PcdChip##id##MppBaseAddress)
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#define GET_REV_FLAG(id) PcdGetBool(PcdChip##id##MppReverseFlag)
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/* We get chip number */
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#define GetMppPcd(id) { \
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PinCount[id] = GET_PIN_COUNT(id); \
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MppRegPcd[id][7] = GET_PCD_PTR(id,7); \
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MppRegPcd[id][6] = GET_PCD_PTR(id,6); \
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MppRegPcd[id][5] = GET_PCD_PTR(id,5); \
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MppRegPcd[id][4] = GET_PCD_PTR(id,4); \
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MppRegPcd[id][3] = GET_PCD_PTR(id,3); \
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MppRegPcd[id][2] = GET_PCD_PTR(id,2); \
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MppRegPcd[id][1] = GET_PCD_PTR(id,1); \
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MppRegPcd[id][0] = GET_PCD_PTR(id,0); \
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BaseAddr[id] = GET_BASE(id); \
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ReverseFlag[id] = GET_REV_FLAG(id); \
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}
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STATIC
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VOID
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SetRegisterValue (
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UINT8 RegCount,
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UINT8 MppRegPcd[][MPP_PINS_PER_REG],
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UINTN BaseAddr,
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BOOLEAN ReverseFlag
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)
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{
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UINT32 i, j, CtrlVal, CtrlMask, PinIndex;
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INTN Sign;
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Sign = ReverseFlag ? -1 : 1;
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for (i = 0; i < RegCount; i++) {
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CtrlVal = 0;
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CtrlMask = 0;
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for (j = 0; j < MPP_PINS_PER_REG; j++) {
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PinIndex = 7 * (UINTN)ReverseFlag + j * Sign;
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if (MppRegPcd[i][PinIndex] != 0xff) {
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CtrlVal |= MPP_PIN_VAL(PinIndex, MppRegPcd[i][PinIndex]);
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CtrlMask |= MPP_PIN_VAL(PinIndex, 0xf);
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}
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}
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MmioAndThenOr32 (BaseAddr + 4 * i * Sign, ~CtrlMask, CtrlVal);
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}
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}
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STATIC
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/* Transform PCD MPP group format into hardware register format */
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UINT8
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PcdToMppRegs (
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UINTN PinCount,
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UINT8 **MppRegPcd,
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UINT8 MppRegPcdTmp[][MPP_PINS_PER_REG]
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)
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{
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UINT8 PcdGroupCount, MppRegCount;
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UINTN i, j, k, l;
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if (PinCount == 0) {
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return 0;
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}
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PcdGroupCount = PinCount / PCD_PINS_PER_GROUP;
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if ((PinCount % PCD_PINS_PER_GROUP) != 0) {
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PcdGroupCount += 1;
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}
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MppRegCount = PinCount / MPP_PINS_PER_REG;
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if ((PinCount % MPP_PINS_PER_REG) != 0) {
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MppRegCount += 1;
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}
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/* Fill temporary table with data from PCD groups in HW format */
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for (i = 0; i < PcdGroupCount; i++) {
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for (j = 0; j < PCD_PINS_PER_GROUP; j++) {
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k = (PCD_PINS_PER_GROUP * i + j) / MPP_PINS_PER_REG;
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l = (PCD_PINS_PER_GROUP * i + j) % MPP_PINS_PER_REG;
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MppRegPcdTmp[k][l] = (UINT8)MppRegPcd[i][j];
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}
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}
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return MppRegCount;
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}
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STATIC
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VOID
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SetSdMmcPhyMpp (
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UINTN BaseAddr,
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UINT32 Index
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)
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{
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UINTN Size, Offset;
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UINT8 *Ptr;
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UINT32 Reg;
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Size = PcdGetSize(PcdPciESdhci);
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Ptr = (UINT8 *) PcdGetPtr(PcdPciESdhci);
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if (Ptr == NULL || Index >= Size) {
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return;
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}
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/* Check if SDHCI controller is enabled on the HW block */
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if (Ptr[Index] != 1) {
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return;
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}
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/* Choose adequate Offset */
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switch (Index) {
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case 0:
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Offset = SD_MMC_PHY_AP_MPP_OFFSET;
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break;
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default:
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Offset = SD_MMC_PHY_CP0_MPP_OFFSET;
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break;
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}
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/*
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* If there is SDHCI controller on platform, connect SD/MMC PHY to
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* SD/MMC controller insted of using it as MPP multiplexer
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*/
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Reg = MmioRead32 (BaseAddr + Offset);
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Reg &= ~MPP_ON_SDPHY_ENABLE;
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MmioWrite32 (BaseAddr + Offset, Reg);
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}
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EFI_STATUS
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MppInitialize (
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)
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{
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UINTN BaseAddr[MAX_CHIPS], PinCount[MAX_CHIPS], RegCount;
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BOOLEAN ReverseFlag[MAX_CHIPS];
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UINT8 *MppRegPcd[MAX_CHIPS][MPP_MAX_REGS];
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UINT32 i, ChipCount;
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UINT8 TmpMppValue[MPP_MAX_REGS][MPP_PINS_PER_REG];
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ChipCount = PcdGet32 (PcdMppChipCount);
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/* Read all needed PCD for MPP configuration */
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GetMppPcd(0);
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GetMppPcd(1);
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GetMppPcd(2);
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GetMppPcd(3);
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for (i = 0; i < MAX_CHIPS; i++) {
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if (i == ChipCount)
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break;
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RegCount = PcdToMppRegs (PinCount[i], MppRegPcd[i], TmpMppValue);
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SetRegisterValue (RegCount, TmpMppValue, BaseAddr[i], ReverseFlag[i]);
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/*
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* eMMC PHY IP has its own MPP configuration.
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*/
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SetSdMmcPhyMpp (BaseAddr[i], i);
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}
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return EFI_SUCCESS;
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}
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