/********************************************************************************
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Copyright (C) 2016 Marvell International Ltd.
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SPDX-License-Identifier: BSD-2-Clause-Patent
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*******************************************************************************/
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#ifndef __COMPHY_H__
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#define __COMPHY_H__
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#include <Uefi.h>
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#include <Library/ArmLib.h>
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#include <Library/ArmPlatformLib.h>
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#include <Library/DebugLib.h>
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#include <Library/PcdLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/MvComPhyLib.h>
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#include <Library/IoLib.h>
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#include <Library/TimerLib.h>
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#include <Library/UefiBootServicesTableLib.h>
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#include <Protocol/BoardDesc.h>
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#include "ComPhySipSvc.h"
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#define MAX_LANE_OPTIONS 10
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/***** Parsing PCD *****/
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#define GET_LANE_TYPE(id) PcdGetPtr(PcdChip##id##ComPhyTypes)
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#define GET_LANE_SPEED(id) PcdGetPtr(PcdChip##id##ComPhySpeeds)
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#define GET_LANE_INV(id) PcdGetPtr(PcdChip##id##ComPhyInvFlags)
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#define GetComPhyPcd(lane_struct, id) { \
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lane_struct[id].Type = (UINT8 *)GET_LANE_TYPE(id); \
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lane_struct[id].SpeedValue = (UINT8 *)GET_LANE_SPEED(id); \
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lane_struct[id].InvFlag = (UINT8 *)GET_LANE_SPEED(id); \
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}
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#define COMPHY_TYPE_UNCONNECTED 0
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#define COMPHY_TYPE_PCIE0 1
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#define COMPHY_TYPE_PCIE1 2
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#define COMPHY_TYPE_PCIE2 3
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#define COMPHY_TYPE_PCIE3 4
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#define COMPHY_TYPE_SATA0 5
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#define COMPHY_TYPE_SATA1 6
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#define COMPHY_TYPE_SATA2 7
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#define COMPHY_TYPE_SATA3 8
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#define COMPHY_TYPE_SGMII0 9
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#define COMPHY_TYPE_SGMII1 10
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#define COMPHY_TYPE_SGMII2 11
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#define COMPHY_TYPE_SGMII3 12
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#define COMPHY_TYPE_QSGMII 13
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#define COMPHY_TYPE_USB3_HOST0 14
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#define COMPHY_TYPE_USB3_HOST1 15
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#define COMPHY_TYPE_USB3_DEVICE 16
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#define COMPHY_TYPE_XAUI0 17
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#define COMPHY_TYPE_XAUI1 18
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#define COMPHY_TYPE_XAUI2 19
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#define COMPHY_TYPE_XAUI3 20
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#define COMPHY_TYPE_RXAUI0 21
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#define COMPHY_TYPE_RXAUI1 22
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#define COMPHY_TYPE_SFI 23
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#define COMPHY_TYPE_MAX 24
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#define COMPHY_TYPE_INVALID 0xff
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/***** SATA registers *****/
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#define SATA3_VENDOR_ADDRESS 0xA0
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#define SATA3_VENDOR_ADDR_OFSSET 0
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#define SATA3_VENDOR_ADDR_MASK (0xFFFFFFFF << SATA3_VENDOR_ADDR_OFSSET)
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#define SATA3_VENDOR_DATA 0xA4
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#define SATA_CONTROL_REG 0x0
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#define SATA3_CTRL_SATA0_PD_OFFSET 6
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#define SATA3_CTRL_SATA0_PD_MASK (1 << SATA3_CTRL_SATA0_PD_OFFSET)
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#define SATA3_CTRL_SATA1_PD_OFFSET 14
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#define SATA3_CTRL_SATA1_PD_MASK (1 << SATA3_CTRL_SATA1_PD_OFFSET)
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#define SATA3_CTRL_SATA1_ENABLE_OFFSET 22
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#define SATA3_CTRL_SATA1_ENABLE_MASK (1 << SATA3_CTRL_SATA1_ENABLE_OFFSET)
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#define SATA3_CTRL_SATA_SSU_OFFSET 23
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#define SATA3_CTRL_SATA_SSU_MASK (1 << SATA3_CTRL_SATA_SSU_OFFSET)
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#define SATA_MBUS_SIZE_SELECT_REG 0x4
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#define SATA_MBUS_REGRET_EN_OFFSET 7
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#define SATA_MBUS_REGRET_EN_MASK (0x1 << SATA_MBUS_REGRET_EN_OFFSET)
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/***************************/
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typedef struct _CHIP_COMPHY_CONFIG CHIP_COMPHY_CONFIG;
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typedef struct {
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UINT32 Type;
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UINT32 MuxValue;
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} COMPHY_MUX_OPTIONS;
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typedef struct {
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UINT8 Type;
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UINT8 Speed;
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UINT8 Invert;
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} COMPHY_MAP;
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typedef struct {
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UINT8 *Type;
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UINT8 *SpeedValue;
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UINT8 *InvFlag;
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} PCD_LANE_MAP;
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typedef
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VOID
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(*COMPHY_CHIP_INIT) (
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IN CHIP_COMPHY_CONFIG *PtrChipCfg
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);
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struct _CHIP_COMPHY_CONFIG {
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MV_COMPHY_CHIP_TYPE ChipType;
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COMPHY_MAP MapData[MAX_LANE_OPTIONS];
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EFI_PHYSICAL_ADDRESS ComPhyBaseAddr;
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EFI_PHYSICAL_ADDRESS Hpipe3BaseAddr;
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COMPHY_CHIP_INIT Init;
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UINT32 LanesCount;
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UINT32 MuxBitCount;
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UINT8 ChipId;
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};
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VOID
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ComPhyCp110Init (
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IN CHIP_COMPHY_CONFIG * First
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);
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VOID
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RegSet (
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IN EFI_PHYSICAL_ADDRESS Addr,
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IN UINT32 Data,
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IN UINT32 Mask
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);
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VOID
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RegSetSilent (
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IN EFI_PHYSICAL_ADDRESS Addr,
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IN UINT32 Data,
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IN UINT32 Mask
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);
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#endif // __COMPHY_H__
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