/********************************************************************************
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Copyright (C) 2016 Marvell International Ltd.
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SPDX-License-Identifier: BSD-2-Clause-Patent
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*******************************************************************************/
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#include "ComPhyLib.h"
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#include <Library/MvComPhyLib.h>
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CHAR16 * TypeStringTable [] = {L"unconnected", L"PCIE0", L"PCIE1", L"PCIE2",
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L"PCIE3", L"SATA0", L"SATA1", L"SATA2", L"SATA3",
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L"SGMII0", L"SGMII1", L"SGMII2", L"SGMII3",
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L"QSGMII", L"USB3_HOST0", L"USB3_HOST1",
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L"USB3_DEVICE", L"XAUI0", L"XAUI1", L"XAUI2",
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L"XAUI3", L"RXAUI0", L"RXAUI1", L"SFI"};
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CHAR16 * SpeedStringTable [] = {L"1.25 Gbps", L"2.5 Gbps", L"3.125 Gbps",
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L"5 Gbps", L"5.156 Gbps", L"6 Gbps",
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L"10.31 Gbps"};
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CHIP_COMPHY_CONFIG ChipCfgTbl[] = {
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{
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.ChipType = MvComPhyTypeCp110,
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.Init = ComPhyCp110Init
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},
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};
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VOID
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RegSet (
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IN EFI_PHYSICAL_ADDRESS Addr,
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IN UINT32 Data,
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IN UINT32 Mask
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)
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{
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DEBUG((DEBUG_INFO, "Write to address = %10x, data = %10x (mask = %10x)"
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"- ", Addr, Data, Mask));
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DEBUG((DEBUG_INFO, "old value = %10x ==> ", MmioRead32 (Addr)));
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RegSetSilent (Addr, Data, Mask);
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DEBUG((DEBUG_INFO, "new value %10x\n", MmioRead32 (Addr)));
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}
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VOID
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RegSetSilent (
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IN EFI_PHYSICAL_ADDRESS Addr,
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IN UINT32 Data,
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IN UINT32 Mask
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)
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{
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UINT32 RegData;
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RegData = MmioRead32 (Addr);
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RegData &= ~Mask;
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RegData |= Data;
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MmioWrite32 (Addr, RegData);
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}
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CHAR16 *
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GetTypeString (
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UINT32 Type
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)
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{
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if (Type < 0 || Type > COMPHY_TYPE_MAX) {
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return L"invalid";
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}
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return TypeStringTable[Type];
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}
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CHAR16 *
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GetSpeedString (
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UINT32 Speed
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)
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{
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if (Speed == COMPHY_SPEED_DEFAULT) {
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return L"default";
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}
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if (Speed < 0 || Speed > COMPHY_SPEED_MAX) {
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return L"invalid";
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}
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return SpeedStringTable[Speed];
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}
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VOID
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ComPhyPrint (
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IN CHIP_COMPHY_CONFIG *PtrChipCfg,
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IN UINT8 Index
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)
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{
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UINT32 Lane;
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CHAR16 *SpeedStr, *TypeStr;
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for (Lane = 0; Lane < PtrChipCfg->LanesCount; Lane++) {
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SpeedStr = GetSpeedString(PtrChipCfg->MapData[Lane].Speed);
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TypeStr = GetTypeString(PtrChipCfg->MapData[Lane].Type);
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DEBUG ((DEBUG_ERROR, "Comphy%d-%d: %-13s %-10s\n", Index, Lane, TypeStr, SpeedStr));
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}
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DEBUG((DEBUG_ERROR, "\n"));
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}
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EFI_STATUS
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GetChipComPhyInit (
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IN CHIP_COMPHY_CONFIG *PtrChipCfg
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)
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{
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UINTN i, TblSize;
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TblSize = sizeof(ChipCfgTbl) / sizeof(ChipCfgTbl[0]);
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for (i = 0; i < TblSize ; i++) {
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if (PtrChipCfg->ChipType == ChipCfgTbl[i].ChipType) {
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PtrChipCfg->Init = ChipCfgTbl[i].Init;
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return EFI_SUCCESS;
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}
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}
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return EFI_D_ERROR;
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}
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STATIC
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VOID
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InitComPhyConfig (
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IN OUT CHIP_COMPHY_CONFIG *ChipConfig,
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IN OUT PCD_LANE_MAP *LaneData,
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IN MV_BOARD_COMPHY_DESC *Desc
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)
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{
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ChipConfig->ChipType = Desc->SoC->ComPhyChipType;
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ChipConfig->ComPhyBaseAddr = Desc->SoC->ComPhyBaseAddress;
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ChipConfig->Hpipe3BaseAddr = Desc->SoC->ComPhyHpipe3BaseAddress;
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ChipConfig->LanesCount = Desc->SoC->ComPhyLaneCount;
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ChipConfig->MuxBitCount = Desc->SoC->ComPhyMuxBitCount;
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ChipConfig->ChipId = Desc->SoC->ComPhyId;
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/*
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* Below macro contains variable name concatenation (used to form PCD's name).
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*/
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switch (ChipConfig->ChipId) {
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case 0:
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GetComPhyPcd (LaneData, 0);
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break;
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case 1:
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GetComPhyPcd (LaneData, 1);
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break;
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case 2:
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GetComPhyPcd (LaneData, 2);
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break;
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case 3:
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GetComPhyPcd (LaneData, 3);
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break;
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}
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}
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EFI_STATUS
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MvComPhyInit (
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VOID
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)
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{
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EFI_STATUS Status;
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CHIP_COMPHY_CONFIG *ChipConfig, *PtrChipCfg;
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MARVELL_BOARD_DESC_PROTOCOL *BoardDescProtocol;
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MV_BOARD_COMPHY_DESC *ComPhyBoardDesc;
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PCD_LANE_MAP *LaneData;
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UINT32 Lane, MaxComphyCount;
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UINTN Index;
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/* Obtain table with enabled ComPhy devices */
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Status = gBS->LocateProtocol (&gMarvellBoardDescProtocolGuid,
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NULL,
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(VOID **)&BoardDescProtocol);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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Status = BoardDescProtocol->BoardDescComPhyGet (BoardDescProtocol,
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&ComPhyBoardDesc);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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ChipConfig = AllocateZeroPool (ComPhyBoardDesc->ComPhyDevCount *
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sizeof (CHIP_COMPHY_CONFIG));
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if (ChipConfig == NULL) {
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DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__));
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BoardDescProtocol->BoardDescFree (ComPhyBoardDesc);
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return EFI_OUT_OF_RESOURCES;
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}
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LaneData = AllocateZeroPool (ComPhyBoardDesc->ComPhyDevCount *
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sizeof (PCD_LANE_MAP));
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if (ChipConfig == NULL) {
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DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__));
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BoardDescProtocol->BoardDescFree (ComPhyBoardDesc);
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FreePool (ChipConfig);
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return EFI_OUT_OF_RESOURCES;
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}
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/* Initialize enabled chips */
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for (Index = 0; Index < ComPhyBoardDesc->ComPhyDevCount; Index++) {
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PtrChipCfg = &ChipConfig[Index];
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InitComPhyConfig (PtrChipCfg, LaneData, &ComPhyBoardDesc[Index]);
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/* Get the count of the SerDes of the specific chip */
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MaxComphyCount = PtrChipCfg->LanesCount;
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for (Lane = 0; Lane < MaxComphyCount; Lane++) {
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PtrChipCfg->MapData[Lane].Type = LaneData[Index].Type[Lane];
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PtrChipCfg->MapData[Lane].Speed = LaneData[Index].SpeedValue[Lane];
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PtrChipCfg->MapData[Lane].Invert = LaneData[Index].InvFlag[Lane];
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if ((PtrChipCfg->MapData[Lane].Speed == COMPHY_SPEED_INVALID) ||
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(PtrChipCfg->MapData[Lane].Type == COMPHY_TYPE_INVALID)) {
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DEBUG((DEBUG_ERROR, "ComPhy: No valid phy speed or type for lane %d, "
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"setting lane as unconnected\n", Lane + 1));
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PtrChipCfg->MapData[Lane].Type = COMPHY_TYPE_UNCONNECTED;
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PtrChipCfg->MapData[Lane].Speed = COMPHY_SPEED_INVALID;
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}
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};
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Status = GetChipComPhyInit (PtrChipCfg);
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if (EFI_ERROR(Status)) {
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DEBUG ((DEBUG_ERROR, "ComPhy: Invalid Chip%d type\n", Index));
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return Status;
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}
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ComPhyPrint (PtrChipCfg, Index);
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/* PHY power UP sequence */
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PtrChipCfg->Init (PtrChipCfg);
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}
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BoardDescProtocol->BoardDescFree (ComPhyBoardDesc);
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FreePool (ChipConfig);
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FreePool (LaneData);
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return EFI_SUCCESS;
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}
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