/********************************************************************************
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Copyright (C) 2016 Marvell International Ltd.
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SPDX-License-Identifier: BSD-2-Clause-Patent
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*******************************************************************************/
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#include "ComPhyLib.h"
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#include <Library/ArmSmcLib.h>
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#include <Library/SampleAtResetLib.h>
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#include <IndustryStandard/ArmStdSmc.h>
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#define SD_LANE_ADDR_WIDTH 0x1000
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#define HPIPE_ADDR_OFFSET 0x800
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#define COMPHY_ADDR_LANE_WIDTH 0x28
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#define SD_ADDR(base, Lane) (base + SD_LANE_ADDR_WIDTH * Lane)
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#define HPIPE_ADDR(base, Lane) (SD_ADDR(base, Lane) + HPIPE_ADDR_OFFSET)
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#define COMPHY_ADDR(base, Lane) (base + COMPHY_ADDR_LANE_WIDTH * Lane)
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STATIC
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VOID
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ComPhySataMacPowerDown (
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IN EFI_PHYSICAL_ADDRESS SataBase
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)
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{
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UINT32 Mask, Data;
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/*
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* MAC configuration - power down ComPhy
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* Use indirect address for vendor specific SATA control register
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*/
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RegSet (SataBase + SATA3_VENDOR_ADDRESS,
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SATA_CONTROL_REG << SATA3_VENDOR_ADDR_OFSSET, SATA3_VENDOR_ADDR_MASK);
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/* SATA 0 power down */
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Mask = SATA3_CTRL_SATA0_PD_MASK;
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Data = 0x1 << SATA3_CTRL_SATA0_PD_OFFSET;
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/* SATA 1 power down */
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Mask |= SATA3_CTRL_SATA1_PD_MASK;
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Data |= 0x1 << SATA3_CTRL_SATA1_PD_OFFSET;
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/* SATA SSU disable */
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Mask |= SATA3_CTRL_SATA1_ENABLE_MASK;
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Data |= 0x0 << SATA3_CTRL_SATA1_ENABLE_OFFSET;
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/* SATA port 1 disable */
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Mask |= SATA3_CTRL_SATA_SSU_MASK;
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Data |= 0x0 << SATA3_CTRL_SATA_SSU_OFFSET;
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RegSet (SataBase + SATA3_VENDOR_DATA, Data, Mask);
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}
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STATIC
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VOID
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ComPhySataPhyPowerUp (
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IN EFI_PHYSICAL_ADDRESS SataBase
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)
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{
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UINT32 Data, Mask;
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/*
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* MAC configuration - power up ComPhy - power up PLL/TX/RX
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* Use indirect address for vendor specific SATA control register
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*/
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RegSet (SataBase + SATA3_VENDOR_ADDRESS,
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SATA_CONTROL_REG << SATA3_VENDOR_ADDR_OFSSET, SATA3_VENDOR_ADDR_MASK);
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/* SATA 0 power up */
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Mask = SATA3_CTRL_SATA0_PD_MASK;
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Data = 0x0 << SATA3_CTRL_SATA0_PD_OFFSET;
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/* SATA 1 power up */
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Mask |= SATA3_CTRL_SATA1_PD_MASK;
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Data |= 0x0 << SATA3_CTRL_SATA1_PD_OFFSET;
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/* SATA SSU enable */
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Mask |= SATA3_CTRL_SATA1_ENABLE_MASK;
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Data |= 0x1 << SATA3_CTRL_SATA1_ENABLE_OFFSET;
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/* SATA port 1 enable */
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Mask |= SATA3_CTRL_SATA_SSU_MASK;
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Data |= 0x1 << SATA3_CTRL_SATA_SSU_OFFSET;
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RegSet (SataBase + SATA3_VENDOR_DATA, Data, Mask);
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/* MBUS request size and interface select register */
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RegSet (SataBase + SATA3_VENDOR_ADDRESS,
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SATA_MBUS_SIZE_SELECT_REG << SATA3_VENDOR_ADDR_OFSSET,
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SATA3_VENDOR_ADDR_MASK);
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/* Mbus regret enable */
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RegSet (SataBase + SATA3_VENDOR_DATA, 0x1 << SATA_MBUS_REGRET_EN_OFFSET,
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SATA_MBUS_REGRET_EN_MASK);
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}
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STATIC
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EFI_STATUS
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ComPhySmc (
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IN UINT32 FunctionId,
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EFI_PHYSICAL_ADDRESS ComPhyBaseAddr,
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IN UINT32 Lane,
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IN UINT32 Mode
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)
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{
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ARM_SMC_ARGS SmcRegs = {0};
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SmcRegs.Arg0 = FunctionId;
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SmcRegs.Arg1 = (UINTN)ComPhyBaseAddr;
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SmcRegs.Arg2 = Lane;
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SmcRegs.Arg3 = Mode;
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ArmCallSmc (&SmcRegs);
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if (SmcRegs.Arg0 != 0) {
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return EFI_DEVICE_ERROR;
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}
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return EFI_SUCCESS;
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}
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STATIC
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UINTN
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ComPhySataPowerUp (
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IN UINTN ChipId,
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IN UINT32 Lane,
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IN EFI_PHYSICAL_ADDRESS HpipeBase,
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IN EFI_PHYSICAL_ADDRESS ComPhyBase,
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IN MV_BOARD_AHCI_DESC *Desc
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)
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{
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EFI_STATUS Status;
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DEBUG ((DEBUG_INFO, "ComPhySata: Initialize SATA PHYs\n"));
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DEBUG((DEBUG_INFO, "ComPhySataPowerUp: stage: MAC configuration - power down ComPhy\n"));
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ComPhySataMacPowerDown (Desc[ChipId].SoC->AhciBaseAddress);
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Status = ComPhySmc (MV_SMC_ID_COMPHY_POWER_ON,
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ComPhyBase,
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Lane,
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COMPHY_FW_FORMAT (COMPHY_SATA_MODE,
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Desc[ChipId].SoC->AhciId,
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COMPHY_SPEED_DEFAULT));
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if (EFI_ERROR (Status)) {
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return Status;
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}
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ComPhySataPhyPowerUp (Desc[ChipId].SoC->AhciBaseAddress);
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Status = ComPhySmc (MV_SMC_ID_COMPHY_PLL_LOCK,
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ComPhyBase,
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Lane,
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COMPHY_FW_FORMAT (COMPHY_SATA_MODE,
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Desc[ChipId].SoC->AhciId,
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COMPHY_SPEED_DEFAULT));
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if (EFI_ERROR (Status)) {
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return Status;
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}
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return Status;
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}
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VOID
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ComPhyCp110Init (
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IN CHIP_COMPHY_CONFIG *PtrChipCfg
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)
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{
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EFI_STATUS Status;
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COMPHY_MAP *PtrComPhyMap, *SerdesMap;
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EFI_PHYSICAL_ADDRESS ComPhyBaseAddr, HpipeBaseAddr;
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MARVELL_BOARD_DESC_PROTOCOL *BoardDescProtocol;
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MV_BOARD_AHCI_DESC *AhciBoardDesc;
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UINT32 ComPhyMaxCount, Lane;
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UINT32 PcieWidth = 0;
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UINT8 ChipId;
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ComPhyMaxCount = PtrChipCfg->LanesCount;
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ComPhyBaseAddr = PtrChipCfg->ComPhyBaseAddr;
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HpipeBaseAddr = PtrChipCfg->Hpipe3BaseAddr;
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SerdesMap = PtrChipCfg->MapData;
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ChipId = PtrChipCfg->ChipId;
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/* Check if the first 4 Lanes configured as By-4 */
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for (Lane = 0, PtrComPhyMap = SerdesMap; Lane < 4; Lane++, PtrComPhyMap++) {
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if (PtrComPhyMap->Type != COMPHY_TYPE_PCIE0) {
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break;
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}
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PcieWidth++;
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}
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for (Lane = 0, PtrComPhyMap = SerdesMap; Lane < ComPhyMaxCount;
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Lane++, PtrComPhyMap++) {
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DEBUG((DEBUG_INFO, "ComPhy: Initialize serdes number %d\n", Lane));
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DEBUG((DEBUG_INFO, "ComPhy: Serdes Type = 0x%x\n", PtrComPhyMap->Type));
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if (Lane >= 4) {
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/* PCIe lanes above the first 4 lanes, can be only by1 */
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PcieWidth = 1;
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}
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switch (PtrComPhyMap->Type) {
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case COMPHY_TYPE_UNCONNECTED:
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continue;
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break;
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case COMPHY_TYPE_PCIE0:
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case COMPHY_TYPE_PCIE1:
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case COMPHY_TYPE_PCIE2:
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case COMPHY_TYPE_PCIE3:
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Status = ComPhySmc (MV_SMC_ID_COMPHY_POWER_ON,
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PtrChipCfg->ComPhyBaseAddr,
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Lane,
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COMPHY_FW_PCIE_FORMAT (PcieWidth,
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COMPHY_PCIE_MODE,
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PtrComPhyMap->Speed));
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break;
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case COMPHY_TYPE_SATA0:
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case COMPHY_TYPE_SATA1:
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case COMPHY_TYPE_SATA2:
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case COMPHY_TYPE_SATA3:
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/* Obtain AHCI board description */
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Status = gBS->LocateProtocol (&gMarvellBoardDescProtocolGuid,
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NULL,
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(VOID **)&BoardDescProtocol);
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if (EFI_ERROR (Status)) {
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break;
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}
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Status = BoardDescProtocol->BoardDescAhciGet (BoardDescProtocol,
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&AhciBoardDesc);
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if (EFI_ERROR (Status)) {
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break;
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}
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Status = ComPhySataPowerUp (ChipId,
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Lane,
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HpipeBaseAddr,
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ComPhyBaseAddr,
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AhciBoardDesc);
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BoardDescProtocol->BoardDescFree (AhciBoardDesc);
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break;
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case COMPHY_TYPE_USB3_HOST0:
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case COMPHY_TYPE_USB3_HOST1:
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Status = ComPhySmc (MV_SMC_ID_COMPHY_POWER_ON,
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PtrChipCfg->ComPhyBaseAddr,
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Lane,
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COMPHY_FW_MODE_FORMAT (COMPHY_USB3H_MODE));
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break;
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case COMPHY_TYPE_SGMII0:
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case COMPHY_TYPE_SGMII1:
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case COMPHY_TYPE_SGMII2:
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case COMPHY_TYPE_SGMII3:
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Status = ComPhySmc (MV_SMC_ID_COMPHY_POWER_ON,
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PtrChipCfg->ComPhyBaseAddr,
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Lane,
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COMPHY_FW_FORMAT (COMPHY_SGMII_MODE,
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(PtrComPhyMap->Type - COMPHY_TYPE_SGMII0),
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PtrComPhyMap->Speed));
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break;
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case COMPHY_TYPE_SFI:
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Status = ComPhySmc (MV_SMC_ID_COMPHY_POWER_ON,
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PtrChipCfg->ComPhyBaseAddr,
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Lane,
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COMPHY_FW_FORMAT (COMPHY_SFI_MODE,
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COMPHY_UNIT_ID0,
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PtrComPhyMap->Speed));
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break;
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case COMPHY_TYPE_RXAUI0:
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case COMPHY_TYPE_RXAUI1:
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Status = ComPhySmc (MV_SMC_ID_COMPHY_POWER_ON,
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PtrChipCfg->ComPhyBaseAddr,
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Lane,
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COMPHY_FW_MODE_FORMAT (COMPHY_RXAUI_MODE));
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break;
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default:
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DEBUG((DEBUG_ERROR, "Unknown SerDes Type, skip initialize SerDes %d\n",
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Lane));
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Status = EFI_INVALID_PARAMETER;
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ASSERT (FALSE);
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break;
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}
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if (EFI_ERROR(Status)) {
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DEBUG ((DEBUG_ERROR, "Failed to initialize Lane %d\n with Status = 0x%x", Lane, Status));
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PtrComPhyMap->Type = COMPHY_TYPE_UNCONNECTED;
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}
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}
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}
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