/**
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*
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* Copyright (C) 2018, Marvell International Ltd. and its affiliates
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*
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* SPDX-License-Identifier: BSD-2-Clause-Patent
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*
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**/
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#ifndef __ARMADA_SOC_DESC_LIB_H__
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#define __ARMADA_SOC_DESC_LIB_H__
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#include <Library/MvComPhyLib.h>
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#include <Library/NonDiscoverableDeviceRegistrationLib.h>
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#include <Protocol/EmbeddedGpio.h>
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//
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// North Bridge description
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//
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/**
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Routine Description:
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Get base address of the SoC North Bridge.
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Arguments:
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ApBase - Base address of the North Bridge.
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ApIndex - Index of the North Bridge.
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Returns:
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EFI_SUCCESS - Proper base address is returned.
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EFI_INVALID_PARAMETER - The index is out of range.
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**/
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EFI_STATUS
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EFIAPI
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ArmadaSoCAp8xxBaseGet (
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IN OUT EFI_PHYSICAL_ADDRESS *ApBase,
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IN UINTN ApIndex
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);
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//
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// ComPhy SoC description
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//
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typedef struct {
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UINTN ComPhyId;
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UINTN ComPhyBaseAddress;
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UINTN ComPhyHpipe3BaseAddress;
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UINTN ComPhyLaneCount;
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UINTN ComPhyMuxBitCount;
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MV_COMPHY_CHIP_TYPE ComPhyChipType;
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} MV_SOC_COMPHY_DESC;
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EFI_STATUS
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EFIAPI
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ArmadaSoCDescComPhyGet (
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IN OUT MV_SOC_COMPHY_DESC **ComPhyDesc,
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IN OUT UINTN *DescCount
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);
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//
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// South Bridge description
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//
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EFI_PHYSICAL_ADDRESS
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EFIAPI
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ArmadaSoCDescCpBaseGet (
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IN UINTN CpIndex
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);
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//
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// GPIO devices description template definition
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//
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EFI_STATUS
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EFIAPI
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ArmadaSoCGpioGet (
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IN OUT GPIO_CONTROLLER **SoCGpioDescription,
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IN OUT UINTN *Count
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);
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//
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// I2C
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//
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typedef struct {
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UINTN I2cId;
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UINTN I2cBaseAddress;
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} MV_SOC_I2C_DESC;
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EFI_STATUS
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EFIAPI
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ArmadaSoCDescI2cGet (
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IN OUT MV_SOC_I2C_DESC **I2cDesc,
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IN OUT UINTN *DescCount
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);
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//
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// ICU (Interrupt Consolidation Unit)
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//
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typedef enum {
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IcuGroupNsr = 0,
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IcuGroupSr = 1,
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IcuGroupLpi = 2,
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IcuGroupVlpi = 3,
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IcuGroupSei = 4,
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IcuGroupRei = 5,
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IcuGroupMax,
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} ICU_GROUP;
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typedef struct {
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ICU_GROUP Group;
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EFI_PHYSICAL_ADDRESS SetSpiAddr;
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EFI_PHYSICAL_ADDRESS ClrSpiAddr;
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} ICU_MSI;
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typedef struct {
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UINTN IcuSpiBase;
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ICU_MSI IcuMsi[IcuGroupMax];
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} MV_SOC_ICU_DESC;
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EFI_STATUS
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EFIAPI
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ArmadaSoCDescIcuGet (
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IN OUT MV_SOC_ICU_DESC **IcuDesc
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);
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//
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// MDIO
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//
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typedef struct {
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UINTN MdioId;
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UINTN MdioBaseAddress;
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} MV_SOC_MDIO_DESC;
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EFI_STATUS
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EFIAPI
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ArmadaSoCDescMdioGet (
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IN OUT MV_SOC_MDIO_DESC **MdioDesc,
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IN OUT UINTN *DescCount
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);
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//
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// NonDiscoverable devices SoC description
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//
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// AHCI
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typedef struct {
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UINTN AhciId;
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UINTN AhciBaseAddress;
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UINTN AhciMemSize;
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NON_DISCOVERABLE_DEVICE_DMA_TYPE AhciDmaType;
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} MV_SOC_AHCI_DESC;
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EFI_STATUS
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EFIAPI
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ArmadaSoCDescAhciGet (
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IN OUT MV_SOC_AHCI_DESC **AhciDesc,
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IN OUT UINTN *DescCount
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);
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// SDMMC
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typedef struct {
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UINTN SdMmcBaseAddress;
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UINTN SdMmcMemSize;
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NON_DISCOVERABLE_DEVICE_DMA_TYPE SdMmcDmaType;
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} MV_SOC_SDMMC_DESC;
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EFI_STATUS
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EFIAPI
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ArmadaSoCDescSdMmcGet (
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IN OUT MV_SOC_SDMMC_DESC **SdMmcDesc,
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IN OUT UINTN *DescCount
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);
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// XHCI
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typedef struct {
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UINTN XhciBaseAddress;
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UINTN XhciMemSize;
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NON_DISCOVERABLE_DEVICE_DMA_TYPE XhciDmaType;
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} MV_SOC_XHCI_DESC;
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EFI_STATUS
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EFIAPI
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ArmadaSoCDescXhciGet (
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IN OUT MV_SOC_XHCI_DESC **XhciDesc,
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IN OUT UINTN *DescCount
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);
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/**
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This function returns the total number of PCIE controllers and an array
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with their base addresses.
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@param[in out] **PcieDbiAddresses Array containing PCIE controllers' base
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adresses.
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@param[in out] *Count Total amount of available PCIE controllers.
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@retval EFI_SUCCESS The data were obtained successfully.
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@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
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lack of resources.
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**/
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EFI_STATUS
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EFIAPI
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ArmadaSoCPcieGet (
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IN OUT EFI_PHYSICAL_ADDRESS **PcieDbiAddresses,
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IN OUT UINTN *Count
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);
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//
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// PP2 NIC devices SoC description
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//
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typedef struct {
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UINTN Pp2BaseAddress;
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UINTN Pp2ClockFrequency;
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} MV_SOC_PP2_DESC;
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EFI_STATUS
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EFIAPI
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ArmadaSoCDescPp2Get (
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IN OUT MV_SOC_PP2_DESC **Pp2Desc,
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IN OUT UINTN *DescCount
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);
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//
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// UTMI PHY devices SoC description
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//
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typedef struct {
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UINT8 UtmiPhyId;
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UINTN UtmiBaseAddress;
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UINTN UtmiPllAddress;
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UINTN UtmiConfigAddress;
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UINTN UsbConfigAddress;
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} MV_SOC_UTMI_DESC;
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EFI_STATUS
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EFIAPI
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ArmadaSoCDescUtmiGet (
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IN OUT MV_SOC_UTMI_DESC **UtmiDesc,
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IN OUT UINTN *DescCount
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);
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#endif /* __ARMADA_SOC_DESC_LIB_H__ */
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