/**
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*
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* Copyright (C) 2018, Marvell International Ltd. and its affiliates
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*
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* SPDX-License-Identifier: BSD-2-Clause-Patent
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*
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**/
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#ifndef __ARMADA_BOARD_DESC_LIB_H__
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#define __ARMADA_BOARD_DESC_LIB_H__
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#include <Library/ArmadaSoCDescLib.h>
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#include <Library/MvGpioLib.h>
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//
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// General purpose routine for per-board initalization
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//
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EFI_STATUS
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EFIAPI
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ArmadaBoardInit (
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VOID
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);
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//
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// COMPHY controllers per-board description
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//
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typedef struct {
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MV_SOC_COMPHY_DESC *SoC;
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UINTN ComPhyDevCount;
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} MV_BOARD_COMPHY_DESC;
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//
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// GPIO devices per-board description
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//
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typedef struct {
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UINTN ChipId;
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UINTN I2cAddress;
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UINTN I2cBus;
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} MV_GPIO_EXPANDER;
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typedef struct {
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GPIO_CONTROLLER *SoCGpio;
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UINTN GpioDeviceCount;
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MV_GPIO_EXPANDER *GpioExpanders;
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UINTN GpioExpanderCount;
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} MV_BOARD_GPIO_DESCRIPTION;
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EFI_STATUS
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EFIAPI
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ArmadaBoardGpioExpanderGet (
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IN OUT MV_GPIO_EXPANDER **GpioExpanders,
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IN OUT UINTN *GpioExpanderCount
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);
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//
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// I2C devices per-board description
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//
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typedef struct {
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MV_SOC_I2C_DESC *SoC;
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UINTN I2cDevCount;
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} MV_BOARD_I2C_DESC;
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//
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// MDIO devices per-board description
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//
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typedef struct {
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MV_SOC_MDIO_DESC *SoC;
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UINTN MdioDevCount;
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} MV_BOARD_MDIO_DESC;
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//
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// NonDiscoverableDevices per-board description
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//
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//
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// AHCI devices per-board description
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//
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typedef struct {
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MV_SOC_AHCI_DESC *SoC;
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UINTN AhciDevCount;
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} MV_BOARD_AHCI_DESC;
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//
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// SDMMC devices per-board description
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//
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typedef enum {
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RemovableSlot,
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EmbeddedSlot,
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SharedBusSlot,
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UnknownSlot
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} MV_SDMMC_SLOT_TYPE;
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typedef struct {
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MV_SOC_SDMMC_DESC *SoC;
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UINTN SdMmcDevCount;
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BOOLEAN Xenon1v8Enabled;
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BOOLEAN Xenon8BitBusEnabled;
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BOOLEAN XenonSlowModeEnabled;
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UINT8 XenonTuningStepDivisor;
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MV_SDMMC_SLOT_TYPE SlotType;
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} MV_BOARD_SDMMC_DESC;
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EFI_STATUS
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EFIAPI
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ArmadaBoardDescSdMmcGet (
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OUT UINTN *SdMmcDevCount,
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OUT MV_BOARD_SDMMC_DESC **SdMmcDesc
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);
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//
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// XHCI devices per-board description
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//
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typedef struct {
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MV_SOC_XHCI_DESC *SoC;
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UINTN XhciDevCount;
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} MV_BOARD_XHCI_DESC;
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//
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// PCIE controllers description
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//
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typedef struct {
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EFI_PHYSICAL_ADDRESS PcieDbiAddress;
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EFI_PHYSICAL_ADDRESS ConfigSpaceAddress;
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UINT64 ConfigSpaceSize;
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BOOLEAN HaveResetGpio;
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MV_GPIO_PIN PcieResetGpio;
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UINT64 PcieBusMin;
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UINT64 PcieBusMax;
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UINT64 PcieIoTranslation;
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UINT64 PcieIoWinBase;
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UINT64 PcieIoWinSize;
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UINT64 PcieMmio32Translation;
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UINT64 PcieMmio32WinBase;
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UINT64 PcieMmio32WinSize;
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UINT64 PcieMmio64Translation;
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UINT64 PcieMmio64WinBase;
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UINT64 PcieMmio64WinSize;
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} MV_PCIE_CONTROLLER;
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typedef struct {
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MV_PCIE_CONTROLLER CONST *PcieControllers;
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UINTN PcieControllerCount;
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} MV_BOARD_PCIE_DESCRIPTION;
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/**
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Return the number and description of PCIE controllers used on the platform.
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@param[in out] **PcieControllers Array containing PCIE controllers'
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description.
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@param[in out] *PcieControllerCount Amount of used PCIE controllers.
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@retval EFI_SUCCESS The data were obtained successfully.
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@retval EFI_NOT_FOUND None of the controllers is used.
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@retval other Return error status.
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**/
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EFI_STATUS
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EFIAPI
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ArmadaBoardPcieControllerGet (
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IN OUT MV_PCIE_CONTROLLER CONST **PcieControllers,
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IN OUT UINTN *PcieControllerCount
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);
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//
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// PP2 NIC devices per-board description
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//
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typedef struct {
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MV_SOC_PP2_DESC *SoC;
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UINT8 Pp2DevCount;
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} MV_BOARD_PP2_DESC;
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//
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// UTMI PHY devices per-board description
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//
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typedef struct {
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MV_SOC_UTMI_DESC *SoC;
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UINTN UtmiDevCount;
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UINTN UtmiPortType;
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} MV_BOARD_UTMI_DESC;
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#endif /* __ARMADA_SOC_DESC_LIB_H__ */
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