/*******************************************************************************
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Copyright (C) 2016 Marvell International Ltd.
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SPDX-License-Identifier: BSD-2-Clause-Patent
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*******************************************************************************/
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#include <Uefi.h>
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#include <IndustryStandard/ArmStdSmc.h>
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#include <IndustryStandard/MvSmc.h>
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#include <Library/ArmadaBoardDescLib.h>
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#include <Library/ArmadaSoCDescLib.h>
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#include <Library/ArmPlatformLib.h>
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#include <Library/ArmSmcLib.h>
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#include <Library/DebugLib.h>
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#include <Library/HobLib.h>
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#include <Library/IoLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include "Armada7k8kLibMem.h"
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// The total number of descriptors, including the final "end-of-table" descriptor.
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#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 16
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// DDR attributes
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#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK
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#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
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STATIC ARM_MEMORY_REGION_DESCRIPTOR mVirtualMemoryTable[MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS];
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// Obtain DRAM size basing on register values filled by early firmware.
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STATIC
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UINT64
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GetDramSize (
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IN OUT UINT64 *MemSize
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)
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{
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#if defined(MDE_CPU_AARCH64)
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ARM_SMC_ARGS SmcRegs = {0};
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EFI_STATUS Status;
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SmcRegs.Arg0 = MV_SMC_ID_DRAM_SIZE;
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Status = ArmadaSoCAp8xxBaseGet (&SmcRegs.Arg1, 0);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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ArmCallSmc (&SmcRegs);
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*MemSize = SmcRegs.Arg0;
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#else
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//
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// Use fixed value, as currently there is no support
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// in Armada early firmware for 32-bit SMC
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//
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*MemSize = FixedPcdGet64 (PcdSystemMemorySize);
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#endif
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return EFI_SUCCESS;
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}
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/**
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Return the Virtual Memory Map of your platform
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This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
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@param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
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Virtual Memory mapping. This array must be ended by a zero-filled
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entry
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**/
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VOID
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ArmPlatformGetVirtualMemoryMap (
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IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
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)
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{
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UINTN Index = 0;
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UINT64 MemSize;
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UINT64 MemLowSize;
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UINT64 MemHighStart;
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UINT64 MemHighSize;
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UINT64 ConfigSpaceBaseAddr;
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UINTN PcieControllerCount;
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UINTN PcieIndex;
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MV_PCIE_CONTROLLER CONST *PcieControllers;
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EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes;
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EFI_STATUS Status;
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ASSERT (VirtualMemoryMap != NULL);
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ConfigSpaceBaseAddr = FixedPcdGet64 (PcdConfigSpaceBaseAddress);
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// Obtain total memory size from the hardware.
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Status = GetDramSize (&MemSize);
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if (EFI_ERROR (Status)) {
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MemSize = FixedPcdGet64 (PcdSystemMemorySize);
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DEBUG ((DEBUG_ERROR, "Limit total memory size to %d MB\n", MemSize / 1024 / 1024));
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}
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if (DRAM_REMAP_ENABLED) {
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MemLowSize = MIN (DRAM_REMAP_TARGET, MemSize);
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MemHighStart = (UINT64)DRAM_REMAP_TARGET + DRAM_REMAP_SIZE;
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MemHighSize = MemSize - MemLowSize;
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} else {
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MemLowSize = MIN (ConfigSpaceBaseAddr, MemSize);
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}
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ResourceAttributes = (
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EFI_RESOURCE_ATTRIBUTE_PRESENT |
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EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
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EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
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EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
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EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
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EFI_RESOURCE_ATTRIBUTE_TESTED
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);
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BuildResourceDescriptorHob (
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EFI_RESOURCE_SYSTEM_MEMORY,
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ResourceAttributes,
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FixedPcdGet64 (PcdSystemMemoryBase),
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MemLowSize
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);
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// DDR
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mVirtualMemoryTable[Index].PhysicalBase = FixedPcdGet64 (PcdSystemMemoryBase);
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mVirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdSystemMemoryBase);
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mVirtualMemoryTable[Index].Length = MemLowSize;
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mVirtualMemoryTable[Index].Attributes = DDR_ATTRIBUTES_CACHED;
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// SoC MMIO configuration space
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mVirtualMemoryTable[++Index].PhysicalBase = ConfigSpaceBaseAddr;
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mVirtualMemoryTable[Index].VirtualBase = ConfigSpaceBaseAddr;
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mVirtualMemoryTable[Index].Length = SIZE_4GB - ConfigSpaceBaseAddr;
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mVirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
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// PCIE ECAM
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Status = ArmadaBoardPcieControllerGet (&PcieControllers, &PcieControllerCount);
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ASSERT_EFI_ERROR (Status);
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for (PcieIndex = 0; PcieIndex < PcieControllerCount; PcieIndex++) {
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mVirtualMemoryTable[++Index].PhysicalBase = PcieControllers[PcieIndex].ConfigSpaceAddress;
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mVirtualMemoryTable[Index].VirtualBase = PcieControllers[PcieIndex].ConfigSpaceAddress;
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mVirtualMemoryTable[Index].Length = (PcieControllers[PcieIndex].ConfigSpaceSize == 0) ?
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SIZE_256MB :
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PcieControllers[PcieIndex].ConfigSpaceSize;
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mVirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
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}
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if (MemSize > MemLowSize) {
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//
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// If we have more than MemLowSize worth of DRAM, the remainder will be
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// mapped at the top of the remapped window.
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//
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mVirtualMemoryTable[++Index].PhysicalBase = MemHighStart;
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mVirtualMemoryTable[Index].VirtualBase = MemHighStart;
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mVirtualMemoryTable[Index].Length = MemHighSize;
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mVirtualMemoryTable[Index].Attributes = DDR_ATTRIBUTES_CACHED;
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BuildResourceDescriptorHob (
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EFI_RESOURCE_SYSTEM_MEMORY,
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ResourceAttributes,
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MemHighStart,
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MemHighSize
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);
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}
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// End of Table
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mVirtualMemoryTable[++Index].PhysicalBase = 0;
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mVirtualMemoryTable[Index].VirtualBase = 0;
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mVirtualMemoryTable[Index].Length = 0;
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mVirtualMemoryTable[Index].Attributes = 0;
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ASSERT((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
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*VirtualMemoryMap = mVirtualMemoryTable;
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}
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