/** @file
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Register names for PCH GPIO
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Conventions:
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Prefixes:
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Definitions beginning with "R_" are registers
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Definitions beginning with "B_" are bits within registers
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Definitions beginning with "V_" are meaningful values within the bits
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Definitions beginning with "S_" are register sizes
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Definitions beginning with "N_" are the bit position
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In general, PCH registers are denoted by "_PCH_" in register names
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Registers / bits that are different between PCH generations are denoted by
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_PCH_[generation_name]_" in register/bit names.
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Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit names.
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Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit names.
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e.g., "_PCH_H_", "_PCH_LP_"
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Registers / bits names without _H_ or _LP_ apply for both H and LP.
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Registers / bits that are different between SKUs are denoted by "_[SKU_name]"
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at the end of the register/bit names
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Registers / bits of new devices introduced in a PCH generation will be just named
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as "_PCH_" without [generation_name] inserted.
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@copyright
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Copyright 2013 - 2021 Intel Corporation. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _PCH_REGS_GPIO_H_
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#define _PCH_REGS_GPIO_H_
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#define V_PCH_GPIO_GPP_A_PAD_MAX 24
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#define V_PCH_GPIO_GPP_B_PAD_MAX 24
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#define V_PCH_GPIO_GPP_C_PAD_MAX 24
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#define V_PCH_GPIO_GPP_D_PAD_MAX 24
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#define V_PCH_LP_GPIO_GPP_E_PAD_MAX 24
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#define V_PCH_H_GPIO_GPP_E_PAD_MAX 13
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#define V_PCH_GPIO_GPP_F_PAD_MAX 24
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#define V_PCH_LP_GPIO_GPP_G_PAD_MAX 8
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#define V_PCH_H_GPIO_GPP_G_PAD_MAX 24
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#define V_PCH_H_GPIO_GPP_H_PAD_MAX 24
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#define V_PCH_H_GPIO_GPP_J_PAD_MAX 24
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#define V_PCH_H_GPIO_GPP_K_PAD_MAX 11
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#define V_PCH_H_GPIO_GPP_L_PAD_MAX 20
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#define V_PCH_H_GPIO_GPP_I_PAD_MAX 11
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#define V_PCH_GPIO_GPD_PAD_MAX 12
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#define V_PCH_GPIO_GROUP_MAX 13
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#define V_PCH_H_GPIO_GROUP_MAX V_PCH_GPIO_GROUP_MAX
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#define V_PCH_LP_GPIO_GROUP_MAX 8
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#define PCH_GPIO_NUM_SUPPORTED_GPIS 261
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#define S_GPIO_PCR_GP_SMI_EN 4
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#define S_GPIO_PCR_GP_SMI_STS 4
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///
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/// Groups mapped to 2-tier General Purpose Event will all be under
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/// one master GPE_111 (0x6F)
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///
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#define PCH_GPIO_2_TIER_MASTER_GPE_NUMBER 0x6F
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//
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// GPIO Common Private Configuration Registers
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//
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#define R_GPIO_PCR_REV_ID 0x00
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#define R_GPIO_PCR_CAP_LIST 0x04
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#define R_GPIO_PCR_FAMBAR 0x08
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#define R_GPIO_PCR_PADBAR 0x0C
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#define B_GPIO_PCR_PADBAR 0x0000FFFF
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#define R_GPIO_PCR_MISCCFG 0x10
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#define B_GPIO_PCR_MISCCFG_GPE0_DW2 (BIT19 | BIT18 | BIT17 | BIT16)
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#define N_GPIO_PCR_MISCCFG_GPE0_DW2 16
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#define B_GPIO_PCR_MISCCFG_GPE0_DW1 (BIT15 | BIT14 | BIT13 | BIT12)
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#define N_GPIO_PCR_MISCCFG_GPE0_DW1 12
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#define B_GPIO_PCR_MISCCFG_GPE0_DW0 (BIT11 | BIT10 | BIT9 | BIT8)
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#define N_GPIO_PCR_MISCCFG_GPE0_DW0 8
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#define B_PCH_PCR_GPIO_MISCCFG_IRQ_ROUTE BIT3
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#define N_PCH_PCR_GPIO_MISCCFG_IRQ_ROUTE 3
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#define B_GPIO_PCR_MISCCFG_GPDPCGEN BIT1
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#define B_GPIO_PCR_MISCCFG_GPDLCGEN BIT0
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// SKL PCH-H:
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#define R_PCH_H_PCR_GPIO_MISCSECCFG 0x14
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//
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// GPIO Community 0 Private Configuration Registers
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//
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// SKL PCH-LP
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#define R_PCH_LP_PCR_GPIO_GPP_A_PAD_OWN 0x20
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#define R_PCH_LP_PCR_GPIO_GPP_B_PAD_OWN 0x30
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#define R_PCH_LP_PCR_GPIO_GPP_A_GPI_VWM_EN 0x80
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#define R_PCH_LP_PCR_GPIO_GPP_B_GPI_VWM_EN 0x84
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#define R_PCH_LP_PCR_GPIO_GPP_A_PADCFGLOCK 0xA0
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#define R_PCH_LP_PCR_GPIO_GPP_A_PADCFGLOCKTX 0xA4
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#define R_PCH_LP_PCR_GPIO_GPP_B_PADCFGLOCK 0xA8
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#define R_PCH_LP_PCR_GPIO_GPP_B_PADCFGLOCKTX 0xAC
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// SKX Server PCH
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#define R_PCH_H_PCR_GPIO_GPP_A_PAD_OWN 0x20
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#define R_PCH_H_PCR_GPIO_GPP_B_PAD_OWN 0x2C
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#define R_PCH_H_PCR_GPIO_GPP_F_PAD_OWN 0x38
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#define R_PCH_H_PCR_GPIO_GPP_A_GPI_VWM_EN 0x50
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#define R_PCH_H_PCR_GPIO_GPP_B_GPI_VWM_EN 0x54
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#define R_PCH_H_PCR_GPIO_GPP_F_GPI_VWM_EN 0x58
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#define R_PCH_H_PCR_GPIO_GPP_A_PADCFGLOCK 0x60
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#define R_PCH_H_PCR_GPIO_GPP_A_PADCFGLOCKTX 0x64
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#define R_PCH_H_PCR_GPIO_GPP_B_PADCFGLOCK 0x68
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#define R_PCH_H_PCR_GPIO_GPP_B_PADCFGLOCKTX 0x6C
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#define R_PCH_H_PCR_GPIO_GPP_F_PADCFGLOCK 0x70
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#define R_PCH_H_PCR_GPIO_GPP_F_PADCFGLOCKTX 0x74
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#define R_PCH_H_PCR_GPIO_GPP_F_HOSTSW_OWN 0x88
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#define R_PCH_H_PCR_GPIO_GPP_F_GPI_IS 0x0108
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#define R_PCH_H_PCR_GPIO_GPP_F_GPI_IE 0x0118
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#define R_PCH_H_PCR_GPIO_GPP_F_GPI_GPE_STS 0x0128
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#define R_PCH_H_PCR_GPIO_GPP_F_GPI_GPE_EN 0x0138
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#define R_PCH_H_PCR_GPIO_GPP_F_PADCFG_OFFSET 0x580
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// Common
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#define R_PCH_PCR_GPIO_GPP_A_HOSTSW_OWN 0x80
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#define R_PCH_PCR_GPIO_GPP_B_HOSTSW_OWN 0x84
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#define R_PCH_PCR_GPIO_GPP_A_GPI_IS 0x0100
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#define R_PCH_PCR_GPIO_GPP_B_GPI_IS 0x0104
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#define R_PCH_PCR_GPIO_GPP_A_GPI_IE 0x0110
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#define R_PCH_PCR_GPIO_GPP_B_GPI_IE 0x0114
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#define R_PCH_PCR_GPIO_GPP_A_GPI_GPE_STS 0x0120
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#define R_PCH_PCR_GPIO_GPP_B_GPI_GPE_STS 0x0124
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#define R_PCH_PCR_GPIO_GPP_A_GPI_GPE_EN 0x0130
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#define R_PCH_PCR_GPIO_GPP_B_GPI_GPE_EN 0x0134
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#define R_PCH_PCR_GPIO_GPP_B_SMI_STS 0x0144
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#define R_PCH_PCR_GPIO_GPP_B_SMI_EN 0x0154
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#define R_PCH_PCR_GPIO_GPP_B_NMI_STS 0x0164
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#define R_PCH_PCR_GPIO_GPP_B_NMI_EN 0x0174
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#define R_PCH_PCR_GPIO_GPP_A_PADCFG_OFFSET 0x400
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#define R_PCH_PCR_GPIO_GPP_B_PADCFG_OFFSET 0x4C0
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//
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// GPIO Community 1 Private Configuration Registers
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//
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//SKL PCH-LP:
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#define R_PCH_LP_PCR_GPIO_GPP_C_PAD_OWN 0x20
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#define R_PCH_LP_PCR_GPIO_GPP_D_PAD_OWN 0x30
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#define R_PCH_LP_PCR_GPIO_GPP_E_PAD_OWN 0x40
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#define R_PCH_LP_PCR_GPIO_GPP_C_GPI_VWM_EN 0x80
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#define R_PCH_LP_PCR_GPIO_GPP_D_GPI_VWM_EN 0x84
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#define R_PCH_LP_PCR_GPIO_GPP_E_GPI_VWM_EN 0x88
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#define R_PCH_LP_PCR_GPIO_GPP_C_PADCFGLOCK 0xA0
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#define R_PCH_LP_PCR_GPIO_GPP_C_PADCFGLOCKTX 0xA4
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#define R_PCH_LP_PCR_GPIO_GPP_D_PADCFGLOCK 0xA8
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#define R_PCH_LP_PCR_GPIO_GPP_D_PADCFGLOCKTX 0xAC
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#define R_PCH_LP_PCR_GPIO_GPP_E_PADCFGLOCK 0xB0
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#define R_PCH_LP_PCR_GPIO_GPP_E_PADCFGLOCKTX 0xB4
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//SKL PCH-H:
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#define R_PCH_H_PCR_GPIO_GPP_C_PAD_OWN 0x20
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#define R_PCH_H_PCR_GPIO_GPP_D_PAD_OWN 0x2C
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#define R_PCH_H_PCR_GPIO_GPP_E_PAD_OWN 0x38
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// Server SKX PCH
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#define R_PCH_H_PCR_GPIO_GPP_C_GPI_VWM_EN 0x50
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#define R_PCH_H_PCR_GPIO_GPP_D_GPI_VWM_EN 0x54
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#define R_PCH_H_PCR_GPIO_GPP_E_GPI_VWM_EN 0x58
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#define R_PCH_H_PCR_GPIO_GPP_C_PADCFGLOCK 0x60
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#define R_PCH_H_PCR_GPIO_GPP_C_PADCFGLOCKTX 0x64
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#define R_PCH_H_PCR_GPIO_GPP_D_PADCFGLOCK 0x68
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#define R_PCH_H_PCR_GPIO_GPP_D_PADCFGLOCKTX 0x6C
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#define R_PCH_H_PCR_GPIO_GPP_E_PADCFGLOCK 0x70
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#define R_PCH_H_PCR_GPIO_GPP_E_PADCFGLOCKTX 0x74
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// Common
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#define R_PCH_PCR_GPIO_GPP_C_HOSTSW_OWN 0x80
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#define R_PCH_PCR_GPIO_GPP_D_HOSTSW_OWN 0x84
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#define R_PCH_PCR_GPIO_GPP_E_HOSTSW_OWN 0x88
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#define R_PCH_PCR_GPIO_GPP_C_GPI_IS 0x0100
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#define R_PCH_PCR_GPIO_GPP_D_GPI_IS 0x0104
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#define R_PCH_PCR_GPIO_GPP_E_GPI_IS 0x0108
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#define R_PCH_PCR_GPIO_GPP_C_GPI_IE 0x0110
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#define R_PCH_PCR_GPIO_GPP_D_GPI_IE 0x0114
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#define R_PCH_PCR_GPIO_GPP_E_GPI_IE 0x0114
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#define R_PCH_PCR_GPIO_GPP_C_GPI_GPE_STS 0x0120
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#define R_PCH_PCR_GPIO_GPP_D_GPI_GPE_STS 0x0124
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#define R_PCH_PCR_GPIO_GPP_E_GPI_GPE_STS 0x0128
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#define R_PCH_PCR_GPIO_GPP_C_GPI_GPE_EN 0x0130
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#define R_PCH_PCR_GPIO_GPP_D_GPI_GPE_EN 0x0134
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#define R_PCH_PCR_GPIO_GPP_E_GPI_GPE_EN 0x0138
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#define R_PCH_PCR_GPIO_GPP_C_SMI_STS 0x0140
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#define R_PCH_PCR_GPIO_GPP_D_SMI_STS 0x0144
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#define R_PCH_PCR_GPIO_GPP_E_SMI_STS 0x0148
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#define R_PCH_PCR_GPIO_GPP_C_SMI_EN 0x0150
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#define R_PCH_PCR_GPIO_GPP_D_SMI_EN 0x0154
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#define R_PCH_PCR_GPIO_GPP_E_SMI_EN 0x0158
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#define R_PCH_PCR_GPIO_GPP_C_NMI_STS 0x0160
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#define R_PCH_PCR_GPIO_GPP_D_NMI_STS 0x0164
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#define R_PCH_PCR_GPIO_GPP_E_NMI_STS 0x0168
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#define R_PCH_PCR_GPIO_GPP_C_NMI_EN 0x0170
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#define R_PCH_PCR_GPIO_GPP_D_NMI_EN 0x0174
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#define R_PCH_PCR_GPIO_GPP_E_NMI_EN 0x0178
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// Common:
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#define R_GPIO_PCR_CAP_LIST_1_PWM 0x0200
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#define R_GPIO_PCR_PWMC 0x0204
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#define R_GPIO_PCR_CAP_LIST_2_SER_BLINK 0x0208
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#define R_GPIO_PCR_GP_SER_BLINK 0x020C
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#define B_GPIO_PCR_GP_SER_BLINK 0x1F
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#define R_GPIO_PCR_GP_SER_CMDSTS 0x0210
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#define B_GPIO_PCR_GP_SER_CMDSTS_DLS (BIT23 | BIT22)
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#define N_GPIO_PCR_GP_SER_CMDSTS_DLS 22
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#define B_GPIO_PCR_GP_SER_CMDSTS_DRS 0x003F0000
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#define N_GPIO_PCR_GP_SER_CMDSTS_DRS 16
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#define B_GPIO_PCR_GP_SER_CMDSTS_BUSY BIT8
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#define B_GPIO_PCR_GP_SER_CMDSTS_GO BIT0
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#define R_GPIO_PCR_GP_SER_DATA 0x0210
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// Common:
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#define R_PCH_PCR_GPIO_GPP_C_PADCFG_OFFSET 0x400
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#define R_PCH_PCR_GPIO_GPP_D_PADCFG_OFFSET 0x4C0
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#define R_PCH_PCR_GPIO_GPP_E_PADCFG_OFFSET 0x580
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//
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// GPIO Community 2 Private Configuration Registers
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//
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// SKL PCH-LP
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#define R_PCH_LP_PCR_GPIO_GPD_PAD_OWN 0x20
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#define R_PCH_LP_PCR_GPIO_GPD_GPI_VWM_EN 0x80
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#define R_PCH_LP_PCR_GPIO_GPD_PADCFGLOCK 0xA0
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#define R_PCH_LP_PCR_GPIO_GPD_PADCFGLOCKTX 0xA4
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// SKX Server PCH
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#define R_PCH_H_PCR_GPIO_GPD_PAD_OWN 0x20
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#define R_PCH_H_PCR_GPIO_GPD_GPI_VWM_EN 0x50
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#define R_PCH_H_PCR_GPIO_GPD_PADCFGLOCK 0x60
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#define R_PCH_H_PCR_GPIO_GPD_PADCFGLOCKTX 0x64
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// Common
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#define R_PCH_PCR_GPIO_GPD_HOSTSW_OWN 0x80
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#define R_PCH_PCR_GPIO_GPD_GPI_IS 0x0100
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#define R_PCH_PCR_GPIO_GPD_GPI_IE 0x0110
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#define R_PCH_PCR_GPIO_GPD_GPI_GPE_STS 0x0120
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#define R_PCH_PCR_GPIO_GPD_GPI_GPE_EN 0x0130
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#define R_PCH_PCR_GPIO_GPD_PADCFG_OFFSET 0x400
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//
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// GPIO Community 3 Private Configuration Registers
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//
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// SKL PCH-LP:
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#define R_PCH_LP_PCR_GPIO_GPP_F_PAD_OWN 0x20
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#define R_PCH_LP_PCR_GPIO_GPP_G_PAD_OWN 0x30
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#define R_PCH_LP_PCR_GPIO_GPP_F_GPI_VWM_EN 0x80
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#define R_PCH_LP_PCR_GPIO_GPP_G_GPI_VWM_EN 0x84
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#define R_PCH_LP_PCR_GPIO_GPP_F_PADCFGLOCK 0xA0
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#define R_PCH_LP_PCR_GPIO_GPP_F_PADCFGLOCKTX 0xA4
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#define R_PCH_LP_PCR_GPIO_GPP_G_PADCFGLOCK 0xA8
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#define R_PCH_LP_PCR_GPIO_GPP_G_PADCFGLOCKTX 0xAC
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#define R_PCH_LP_PCR_GPIO_GPP_F_HOSTSW_OWN 0xD0
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#define R_PCH_LP_PCR_GPIO_GPP_G_HOSTSW_OWN 0xD4
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#define R_PCH_LP_PCR_GPIO_GPP_F_GPI_IS 0x0100
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#define R_PCH_LP_PCR_GPIO_GPP_G_GPI_IS 0x0104
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#define R_PCH_LP_PCR_GPIO_GPP_F_GPI_IE 0x0120
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#define R_PCH_LP_PCR_GPIO_GPP_G_GPI_IE 0x0124
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#define R_PCH_LP_PCR_GPIO_GPP_F_GPI_GPE_STS 0x0140
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#define R_PCH_LP_PCR_GPIO_GPP_G_GPI_GPE_STS 0x0144
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#define R_PCH_LP_PCR_GPIO_GPP_F_GPI_GPE_EN 0x0160
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#define R_PCH_LP_PCR_GPIO_GPP_G_GPI_GPE_EN 0x0164
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#define R_PCH_LP_PCR_GPIO_GPP_F_PADCFG_OFFSET 0x400
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#define R_PCH_LP_PCR_GPIO_GPP_G_PADCFG_OFFSET 0x4C0
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// SKX Server PCH
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#define R_PCH_H_PCR_GPIO_GPP_I_PAD_OWN 0x20
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#define R_PCH_H_PCR_GPIO_GPP_I_GPI_VWM_EN 0x50
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#define R_PCH_H_PCR_GPIO_GPP_I_PADCFGLOCK 0x60
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#define R_PCH_H_PCR_GPIO_GPP_I_PADCFGLOCKTX 0x64
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#define R_PCH_H_PCR_GPIO_GPP_I_HOSTSW_OWN 0x80
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#define R_PCH_H_PCR_GPIO_GPP_I_GPI_IS 0x0100
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#define R_PCH_H_PCR_GPIO_GPP_I_GPI_IE 0x0110
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#define R_PCH_H_PCR_GPIO_GPP_I_GPI_GPE_STS 0x0120
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#define R_PCH_H_PCR_GPIO_GPP_I_GPI_GPE_EN 0x0130
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#define R_PCH_H_PCR_GPIO_GPP_I_SMI_STS 0x0140
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#define R_PCH_H_PCR_GPIO_GPP_I_SMI_EN 0x0150
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#define R_PCH_H_PCR_GPIO_GPP_I_NMI_STS 0x0160
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#define R_PCH_H_PCR_GPIO_GPP_I_NMI_EN 0x0170
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#define R_PCH_H_PCR_GPIO_GPP_I_PADCFG_OFFSET 0x400
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//
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// GPIO Community 4 Private Configuration Registers
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//
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// SKX Server PCH
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#define R_PCH_H_PCR_GPIO_GPP_J_PAD_OWN 0x20
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#define R_PCH_H_PCR_GPIO_GPP_K_PAD_OWN 0x2C
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#define R_PCH_H_PCR_GPIO_GPP_J_GPI_VWM_EN 0x50
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#define R_PCH_H_PCR_GPIO_GPP_K_GPI_VWM_EN 0x54
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#define R_PCH_H_PCR_GPIO_GPP_J_PADCFGLOCK 0x60
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#define R_PCH_H_PCR_GPIO_GPP_J_PADCFGLOCKTX 0x64
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#define R_PCH_H_PCR_GPIO_GPP_K_PADCFGLOCK 0x68
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#define R_PCH_H_PCR_GPIO_GPP_K_PADCFGLOCKTX 0x6C
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#define R_PCH_H_PCR_GPIO_GPP_J_HOSTSW_OWN 0x80
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#define R_PCH_H_PCR_GPIO_GPP_K_HOSTSW_OWN 0x84
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#define R_PCH_H_PCR_GPIO_GPP_J_GPI_IS 0x0100
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#define R_PCH_H_PCR_GPIO_GPP_K_GPI_IS 0x0104
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#define R_PCH_H_PCR_GPIO_GPP_J_GPI_IE 0x0110
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#define R_PCH_H_PCR_GPIO_GPP_K_GPI_IE 0x0114
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#define R_PCH_H_PCR_GPIO_GPP_J_GPI_GPE_STS 0x0120
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#define R_PCH_H_PCR_GPIO_GPP_K_GPI_GPE_STS 0x0124
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#define R_PCH_H_PCR_GPIO_GPP_J_GPI_GPE_EN 0x0130
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#define R_PCH_H_PCR_GPIO_GPP_K_GPI_GPE_EN 0x0134
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#define R_PCH_H_PCR_GPIO_GPP_J_PADCFG_OFFSET 0x400
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#define R_PCH_H_PCR_GPIO_GPP_K_PADCFG_OFFSET 0x4C0
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//
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// GPIO Community 5 Private Configuration Registers
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//
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// SKX Server PCH
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#define R_PCH_H_PCR_GPIO_GPP_G_PAD_OWN 0x20
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#define R_PCH_H_PCR_GPIO_GPP_H_PAD_OWN 0x2C
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#define R_PCH_H_PCR_GPIO_GPP_L_PAD_OWN 0x38
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#define R_PCH_H_PCR_GPIO_GPP_G_GPI_VWM_EN 0x50
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#define R_PCH_H_PCR_GPIO_GPP_H_GPI_VWM_EN 0x54
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#define R_PCH_H_PCR_GPIO_GPP_L_GPI_VWM_EN 0x58
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#define R_PCH_H_PCR_GPIO_GPP_G_PADCFGLOCK 0x60
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#define R_PCH_H_PCR_GPIO_GPP_G_PADCFGLOCKTX 0x64
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#define R_PCH_H_PCR_GPIO_GPP_H_PADCFGLOCK 0x68
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#define R_PCH_H_PCR_GPIO_GPP_H_PADCFGLOCKTX 0x6C
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#define R_PCH_H_PCR_GPIO_GPP_L_PADCFGLOCK 0x70
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#define R_PCH_H_PCR_GPIO_GPP_L_PADCFGLOCKTX 0x74
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#define R_PCH_H_PCR_GPIO_GPP_G_HOSTSW_OWN 0x80
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#define R_PCH_H_PCR_GPIO_GPP_H_HOSTSW_OWN 0x84
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#define R_PCH_H_PCR_GPIO_GPP_L_HOSTSW_OWN 0x88
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#define R_PCH_H_PCR_GPIO_GPP_G_GPI_IS 0x0100
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#define R_PCH_H_PCR_GPIO_GPP_H_GPI_IS 0x0104
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#define R_PCH_H_PCR_GPIO_GPP_L_GPI_IS 0x0108
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#define R_PCH_H_PCR_GPIO_GPP_G_GPI_IE 0x0110
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#define R_PCH_H_PCR_GPIO_GPP_H_GPI_IE 0x0114
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#define R_PCH_H_PCR_GPIO_GPP_L_GPI_IE 0x0118
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#define R_PCH_H_PCR_GPIO_GPP_G_GPI_GPE_STS 0x0120
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#define R_PCH_H_PCR_GPIO_GPP_H_GPI_GPE_STS 0x0124
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#define R_PCH_H_PCR_GPIO_GPP_L_GPI_GPE_STS 0x0128
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#define R_PCH_H_PCR_GPIO_GPP_G_GPI_GPE_EN 0x0130
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#define R_PCH_H_PCR_GPIO_GPP_H_GPI_GPE_EN 0x0134
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#define R_PCH_H_PCR_GPIO_GPP_L_GPI_GPE_EN 0x0138
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#define R_PCH_H_PCR_GPIO_GPP_G_PADCFG_OFFSET 0x400
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#define R_PCH_H_PCR_GPIO_GPP_H_PADCFG_OFFSET 0x4C0
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#define R_PCH_H_PCR_GPIO_GPP_L_PADCFG_OFFSET 0x580
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//
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// Define Pad Number
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//
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#define V_GPIO_PAD0 0
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#define V_GPIO_PAD1 1
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#define V_GPIO_PAD2 2
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#define V_GPIO_PAD3 3
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#define V_GPIO_PAD4 4
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#define V_GPIO_PAD5 5
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#define V_GPIO_PAD6 6
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#define V_GPIO_PAD7 7
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#define V_GPIO_PAD8 8
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#define V_GPIO_PAD9 9
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#define V_GPIO_PAD10 10
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#define V_GPIO_PAD11 11
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#define V_GPIO_PAD12 12
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#define V_GPIO_PAD13 13
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#define V_GPIO_PAD14 14
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#define V_GPIO_PAD15 15
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#define V_GPIO_PAD16 16
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#define V_GPIO_PAD17 17
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#define V_GPIO_PAD18 18
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#define V_GPIO_PAD19 19
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#define V_GPIO_PAD20 20
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#define V_GPIO_PAD21 21
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#define V_GPIO_PAD22 22
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#define V_GPIO_PAD23 23
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//
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// Host Software Pad Ownership modes
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//
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#define V_GPIO_PCR_HOSTSW_OWN_ACPI 0x00
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#define V_GPIO_PCR_HOSTSW_OWN_GPIO 0x01
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//
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// Pad Ownership modes
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//
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#define V_GPIO_PCR_PAD_OWN_HOST 0x00
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#define V_GPIO_PCR_PAD_OWN_CSME 0x01
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#define V_GPIO_PCR_PAD_OWN_ISH 0x02
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//
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// Pad Configuration Register DW0
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//
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//Pad Reset Config
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#define B_GPIO_PCR_RST_CONF (BIT31 | BIT30)
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#define N_GPIO_PCR_RST_CONF 30
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#define V_GPIO_PCR_RST_CONF_POW_GOOD 0x00
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#define V_GPIO_PCR_RST_CONF_DEEP_RST 0x01
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#define V_GPIO_PCR_RST_CONF_GPIO_RST 0x02
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#define V_GPIO_PCR_RST_CONF_RESUME_RST 0x03 // Only for GPD Group
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//RX Pad State Select
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#define B_GPIO_PCR_RX_PAD_STATE BIT29
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#define N_GPIO_PCR_RX_PAD_STATE 29
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#define V_GPIO_PCR_RX_PAD_STATE_RAW 0x00
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#define V_GPIO_PCR_RX_PAD_STATE_INT 0x01
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//RX Raw Overrride to 1
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#define B_GPIO_PCR_RX_RAW1 BIT28
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#define N_GPIO_PCR_RX_RAW1 28
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#define V_GPIO_PCR_RX_RAW1_DIS 0x00
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#define V_GPIO_PCR_RX_RAW1_EN 0x01
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//RX Level/Edge Configuration
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#define B_GPIO_PCR_RX_LVL_EDG (BIT26 | BIT25)
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#define N_GPIO_PCR_RX_LVL_EDG 25
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#define V_GPIO_PCR_RX_LVL_EDG_LVL 0x00
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#define V_GPIO_PCR_RX_LVL_EDG_EDG 0x01
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#define V_GPIO_PCR_RX_LVL_EDG_0 0x02
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#define V_GPIO_PCR_RX_LVL_EDG_RIS_FAL 0x03
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//RX Invert
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#define B_GPIO_PCR_RXINV BIT23
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#define N_GPIO_PCR_RXINV 23
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#define V_GPIO_PCR_RXINV_NO 0x00
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#define V_GPIO_PCR_RXINV_YES 0x01
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//GPIO Input Route IOxAPIC
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#define B_GPIO_PCR_RX_APIC_ROUTE BIT20
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#define N_GPIO_PCR_RX_APIC_ROUTE 20
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#define V_GPIO_PCR_RX_APIC_ROUTE_DIS 0x00
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#define V_GPIO_PCR_RX_APIC_ROUTE_EN 0x01
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//GPIO Input Route SCI
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#define B_GPIO_PCR_RX_SCI_ROUTE BIT19
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#define N_GPIO_PCR_RX_SCI_ROUTE 19
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#define V_GPIO_PCR_RX_SCI_ROUTE_DIS 0x00
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#define V_GPIO_PCR_RX_SCI_ROUTE_EN 0x01
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//GPIO Input Route SMI
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#define B_GPIO_PCR_RX_SMI_ROUTE BIT18
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#define N_GPIO_PCR_RX_SMI_ROUTE 18
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#define V_GPIO_PCR_RX_SMI_ROUTE_DIS 0x00
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#define V_GPIO_PCR_RX_SMI_ROUTE_EN 0x01
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//GPIO Input Route NMI
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#define B_GPIO_PCR_RX_NMI_ROUTE BIT17
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#define N_GPIO_PCR_RX_NMI_ROUTE 17
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#define V_GPIO_PCR_RX_NMI_ROUTE_DIS 0x00
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#define V_GPIO_PCR_RX_NMI_ROUTE_EN 0x01
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//GPIO Pad Mode
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#define B_GPIO_PCR_PAD_MODE (BIT12 | BIT11 | BIT10)
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#define N_GPIO_PCR_PAD_MODE 10
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#define V_GPIO_PCR_PAD_MODE_GPIO 0
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#define V_GPIO_PCR_PAD_MODE_NAT_1 1
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#define V_GPIO_PCR_PAD_MODE_NAT_2 2
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#define V_GPIO_PCR_PAD_MODE_NAT_3 3
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#define V_GPIO_PCR_PAD_MODE_NAT_4 4 // SPT-H only
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//GPIO RX Disable
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#define B_GPIO_PCR_RXDIS BIT9
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#define N_GPIO_PCR_RXDIS 9
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#define V_GPIO_PCR_RXDIS_EN 0x00
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#define V_GPIO_PCR_RXDIS_DIS 0x01
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//GPIO TX Disable
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#define B_GPIO_PCR_TXDIS BIT8
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#define N_GPIO_PCR_TXDIS 8
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#define V_GPIO_PCR_TXDIS_EN 0x00
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#define V_GPIO_PCR_TXDIS_DIS 0x01
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//GPIO RX State
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#define B_GPIO_PCR_RX_STATE BIT1
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#define N_GPIO_PCR_RX_STATE 1
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#define V_GPIO_PCR_RX_STATE_LOW 0x00
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#define V_GPIO_PCR_RX_STATE_HIGH 0x01
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//GPIO TX State
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#define B_GPIO_PCR_TX_STATE BIT0
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#define N_GPIO_PCR_TX_STATE 0
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#define V_GPIO_PCR_TX_STATE_LOW 0x00
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#define V_GPIO_PCR_TX_STATE_HIGH 0x01
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//
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// Pad Configuration Register DW1
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//
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//Padtol
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#define B_GPIO_PCR_PADTOL BIT25
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#define N_GPIO_PCR_PADTOL 25
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#define V_GPIO_PCR_PADTOL_NONE 0x00
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#define V_GPIO_PCR_PADTOL_CLEAR 0x00
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#define V_GPIO_PCR_PADTOL_SET 0x01
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//Termination
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#define B_GPIO_PCR_TERM (BIT13 | BIT12 | BIT11 | BIT10)
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#define N_GPIO_PCR_TERM 10
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#define V_GPIO_PCR_TERM_WPD_NONE 0x00
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#define V_GPIO_PCR_TERM_WPD_5K 0x02
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#define V_GPIO_PCR_TERM_WPD_20K 0x04
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#define V_GPIO_PCR_TERM_WPU_NONE 0x08
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#define V_GPIO_PCR_TERM_WPU_1K 0x09
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#define V_GPIO_PCR_TERM_WPU_2K 0x0B
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#define V_GPIO_PCR_TERM_WPU_5K 0x0A
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#define V_GPIO_PCR_TERM_WPU_20K 0x0C
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#define V_GPIO_PCR_TERM_WPU_1K_2K 0x0D
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#define V_GPIO_PCR_TERM_NATIVE 0x0F
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//Interrupt number
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#define B_GPIO_PCR_INTSEL 0x7F
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#define N_GPIO_PCR_INTSEL 0
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//
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// Ownership
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//
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#define V_GPIO_PCR_OWN_GPIO 0x01
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#define V_GPIO_PCR_OWN_ACPI 0x00
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//
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// GPE
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//
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#define V_GPIO_PCR_GPE_EN 0x01
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#define V_GPIO_PCR_GPE_DIS 0x00
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//
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// SMI
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//
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#define V_GPIO_PCR_SMI_EN 0x01
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#define V_GPIO_PCR_SMI_DIS 0x00
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//
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// NMI
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//
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#define V_GPIO_PCR_NMI_EN 0x01
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#define V_GPIO_PCR_NMI_DIS 0x00
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//
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// Reserved: RSVD1
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//
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#define V_PCH_GPIO_RSVD1 0x00
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#endif
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