/** @file
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Register names for PCH DCI device
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Conventions:
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Prefixes:
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Definitions beginning with "R_" are registers
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Definitions beginning with "B_" are bits within registers
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Definitions beginning with "V_" are meaningful values within the bits
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Definitions beginning with "S_" are register sizes
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Definitions beginning with "N_" are the bit position
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In general, PCH registers are denoted by "_PCH_" in register names
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Registers / bits that are different between PCH generations are denoted by
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_PCH_[generation_name]_" in register/bit names.
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Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit names.
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Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit names.
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e.g., "_PCH_H_", "_PCH_LP_"
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Registers / bits names without _H_ or _LP_ apply for both H and LP.
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Registers / bits that are different between SKUs are denoted by "_[SKU_name]"
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at the end of the register/bit names
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Registers / bits of new devices introduced in a PCH generation will be just named
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as "_PCH_" without [generation_name] inserted.
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@copyright
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Copyright 2018 - 2021 Intel Corporation.
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _PCH_REGS_DCI_H_
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#define _PCH_REGS_DCI_H_
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//
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// DCI PCR Registers
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//
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#define R_PCH_PCR_DCI_ECTRL 0x04 ///< DCI Control Register
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#define B_PCH_PCR_DCI_ECTRL_HDCILOCK BIT0 ///< Host DCI lock
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#define B_PCH_PCR_DCI_ECTRL_HDCIEN BIT4 ///< Host DCI enable
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#define R_PCH_PCR_DCI_ECKPWRCTL 0x08 ///< DCI Power Control
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#define R_PCH_PCR_DCI_PCE 0x30 ///< DCI Power Control Enable Register
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#define B_PCH_PCR_DCI_PCE_HAE BIT5 ///< Hardware Autonomous Enable
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#define B_PCH_PCR_DCI_PCE_D3HE BIT2 ///< D3-Hot Enable
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#define B_PCH_PCR_DCI_PCE_I3E BIT1 ///< I3 Enable
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#define B_PCH_PCR_DCI_PCE_PMCRE BIT0 ///< PMC Request Enable
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#endif
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