/** @file
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Sample to provide FSP wrapper related function.
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@copyright
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Copyright 2014 - 2021 Intel Corporation. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <PiPei.h>
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#include <Library/PeiServicesLib.h>
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#include <Library/DebugLib.h>
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#include <Library/HobLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/LargeVariableReadLib.h>
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#include <FspmUpd.h>
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#include <Guid/PlatformInfo.h>
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#include <Ppi/UpiPolicyPpi.h>
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VOID *
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GetFspNvsBuffer (
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VOID
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)
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{
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EFI_STATUS Status;
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UINTN FspNvsBufferSize;
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VOID *FspNvsBufferPtr;
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FspNvsBufferPtr = NULL;
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FspNvsBufferSize = 0;
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Status = GetLargeVariable (L"FspNvsBuffer", &gFspNonVolatileStorageHobGuid, &FspNvsBufferSize, NULL);
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if (Status == EFI_BUFFER_TOO_SMALL) {
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DEBUG ((DEBUG_INFO, "FspNvsBuffer Size = %d\n", FspNvsBufferSize));
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FspNvsBufferPtr = AllocateZeroPool (FspNvsBufferSize);
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if (FspNvsBufferPtr == NULL) {
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DEBUG ((DEBUG_ERROR, "Error: Cannot create FspNvsBuffer, out of memory!\n"));
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ASSERT (FALSE);
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return NULL;
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}
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Status = GetLargeVariable (L"FspNvsBuffer", &gFspNonVolatileStorageHobGuid, &FspNvsBufferSize, FspNvsBufferPtr);
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if (EFI_ERROR (Status)) {
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DEBUG ((DEBUG_ERROR, "Error: Unable to read FspNvsBuffer UEFI variable Status: %r\n", Status));
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ASSERT_EFI_ERROR (Status);
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return NULL;
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}
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return FspNvsBufferPtr;
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} else if (Status == EFI_NOT_FOUND) {
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DEBUG ((DEBUG_INFO, "Cannot create FSP NVS Buffer, UEFI variable does not exist (this is likely a first boot)\n"));
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} else {
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DEBUG ((DEBUG_ERROR, "Error: Unable to read FspNvsBuffer UEFI variable Status: %r\n", Status));
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ASSERT_EFI_ERROR (Status);
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}
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return NULL;
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}
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VOID
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EFIAPI
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UpdateFspmUpdData (
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IN OUT VOID *FspUpdRgnPtr
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)
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{
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FSPM_UPD *FspmUpd;
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EFI_STATUS Status;
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UPI_POLICY_PPI *UpiPolicyPpi;
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KTI_HOST_IN *Upi;
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UINTN Index;
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VOID *FSPTempMem;
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EFI_HOB_GUID_TYPE *GuidHob;
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EFI_PLATFORM_INFO *PlatformInfo;
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GuidHob = GetFirstGuidHob (&gEfiPlatformInfoGuid);
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ASSERT (GuidHob != NULL);
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PlatformInfo = GET_GUID_HOB_DATA(GuidHob);
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Status = PeiServicesLocatePpi (&gUpiSiPolicyPpiGuid, 0, NULL, &UpiPolicyPpi);
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ASSERT_EFI_ERROR(Status);
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Upi = &UpiPolicyPpi->Upi;
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FspmUpd = (FSPM_UPD*)FspUpdRgnPtr;
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FSPTempMem = (VOID *)(UINTN)(PcdGet32(PcdTemporaryRamBase) + PcdGet32(PcdPeiTemporaryRamRcHeapSize));;
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if (FSPTempMem != NULL) {
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FspmUpd->FspmArchUpd.StackBase = (VOID*)(((UINTN)FSPTempMem) & (~0xFFF));
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FspmUpd->FspmArchUpd.StackSize = PcdGet32(PcdFspTemporaryRamSize);
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}
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for (Index = 0; Index < MAX_SOCKET; Index ++) {
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FspmUpd->FspmConfig.BusRatio[Index] = Upi->BusRatio[Index];
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FspmUpd->FspmConfig.KtiFpgaEnable[Index] = Upi->KtiFpgaEnable[Index];
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}
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FspmUpd->FspmConfig.D2KCreditConfig = Upi->D2KCreditConfig;
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FspmUpd->FspmConfig.SnoopThrottleConfig = Upi->SnoopThrottleConfig;
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FspmUpd->FspmConfig.LegacyVgaSoc = Upi->LegacyVgaSoc;
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FspmUpd->FspmConfig.LegacyVgaStack = Upi->LegacyVgaStack;
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FspmUpd->FspmConfig.P2pRelaxedOrdering = Upi->P2pRelaxedOrdering;
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FspmUpd->FspmConfig.SncEn = Upi->SncEn;
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FspmUpd->FspmConfig.UmaClustering = Upi->UmaClustering;
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FspmUpd->FspmConfig.IoDcMode = Upi->IoDcMode;
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FspmUpd->FspmConfig.DegradePrecedence = Upi->DegradePrecedence;
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FspmUpd->FspmConfig.Degrade4SPreference = Upi->Degrade4SPreference;
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FspmUpd->FspmConfig.DirectoryModeEn = Upi->DirectoryModeEn;
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FspmUpd->FspmConfig.XptPrefetchEn = Upi->XptPrefetchEn;
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FspmUpd->FspmConfig.KtiPrefetchEn = Upi->KtiPrefetchEn;
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FspmUpd->FspmConfig.XptRemotePrefetchEn = Upi->XptRemotePrefetchEn;
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FspmUpd->FspmConfig.DdrtQosMode = Upi->DdrtQosMode;
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FspmUpd->FspmConfig.KtiLinkSpeedMode = Upi->KtiLinkSpeedMode;
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FspmUpd->FspmConfig.KtiLinkSpeed = Upi->KtiLinkSpeed;
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FspmUpd->FspmConfig.KtiLinkL0pEn = Upi->KtiLinkL0pEn;
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FspmUpd->FspmConfig.KtiLinkL1En = Upi->KtiLinkL1En;
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FspmUpd->FspmConfig.KtiFailoverEn = Upi->KtiFailoverEn;
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FspmUpd->FspmConfig.KtiLbEn = Upi->KtiLbEn;
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FspmUpd->FspmConfig.KtiCrcMode = Upi->KtiCrcMode;
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FspmUpd->FspmConfig.KtiCpuSktHotPlugEn = Upi->KtiCpuSktHotPlugEn;
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FspmUpd->FspmConfig.KtiCpuSktHotPlugTopology = Upi->KtiCpuSktHotPlugTopology;
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FspmUpd->FspmConfig.KtiSkuMismatchCheck = Upi->KtiSkuMismatchCheck;
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FspmUpd->FspmConfig.IrqThreshold = Upi->IrqThreshold;
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FspmUpd->FspmConfig.TorThresLoctoremNorm = Upi->TorThresLoctoremNorm;
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FspmUpd->FspmConfig.TorThresLoctoremEmpty = Upi->TorThresLoctoremEmpty;
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FspmUpd->FspmConfig.MbeBwCal = Upi->MbeBwCal;
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FspmUpd->FspmConfig.TscSyncEn = Upi->TscSyncEn;
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FspmUpd->FspmConfig.StaleAtoSOptEn = Upi->StaleAtoSOptEn;
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FspmUpd->FspmConfig.LLCDeadLineAlloc = Upi->LLCDeadLineAlloc;
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FspmUpd->FspmConfig.SplitLock = Upi->SplitLock;
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FspmUpd->FspmConfig.mmCfgBase = Upi->mmCfgBase;
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FspmUpd->FspmConfig.mmCfgSize = Upi->mmCfgSize;
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FspmUpd->FspmConfig.mmiohBase = Upi->mmiohBase;
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FspmUpd->FspmConfig.CpuPaLimit = Upi->CpuPaLimit;
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FspmUpd->FspmConfig.highGap = Upi->highGap;
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FspmUpd->FspmConfig.mmiohSize = Upi->mmiohSize;
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FspmUpd->FspmConfig.isocEn = Upi->isocEn;
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FspmUpd->FspmConfig.dcaEn = Upi->dcaEn;
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FspmUpd->FspmConfig.BoardTypeBitmask = Upi->BoardTypeBitmask;
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FspmUpd->FspmConfig.AllLanesPtr = Upi->AllLanesPtr;
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FspmUpd->FspmConfig.PerLanePtr = Upi->PerLanePtr;
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FspmUpd->FspmConfig.AllLanesSizeOfTable = Upi->AllLanesSizeOfTable;
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FspmUpd->FspmConfig.PerLaneSizeOfTable = Upi->PerLaneSizeOfTable;
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FspmUpd->FspmConfig.WaitTimeForPSBP = Upi->WaitTimeForPSBP;
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FspmUpd->FspmConfig.WaSerializationEn = Upi->WaSerializationEn;
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FspmUpd->FspmConfig.KtiInEnableMktme = Upi->KtiInEnableMktme;
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FspmUpd->FspmConfig.BoardId = PlatformInfo->BoardId;
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FspmUpd->FspmArchUpd.NvsBufferPtr = GetFspNvsBuffer ();
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}
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/**
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This function overrides the default configurations in the FSP-S UPD data region.
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@param[in,out] FspUpdRgnPtr A pointer to the UPD data region data strcture.
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**/
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VOID
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EFIAPI
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UpdateFspsUpdData (
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IN OUT VOID *FspUpdRgnPtr
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)
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{
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}
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/**
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Update TempRamExit parameter.
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@note At this point, memory is ready, PeiServices are available to use.
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@return TempRamExit parameter.
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**/
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VOID *
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EFIAPI
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UpdateTempRamExitParam (
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VOID
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)
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{
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return NULL;
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}
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/**
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Get S3 PEI memory information.
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@note At this point, memory is ready, and PeiServices are available to use.
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Platform can get some data from SMRAM directly.
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@param[out] S3PeiMemSize PEI memory size to be installed in S3 phase.
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@param[out] S3PeiMemBase PEI memory base to be installed in S3 phase.
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@return If S3 PEI memory information is got successfully.
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**/
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EFI_STATUS
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EFIAPI
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GetS3MemoryInfo (
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OUT UINT64 *S3PeiMemSize,
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OUT EFI_PHYSICAL_ADDRESS *S3PeiMemBase
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)
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{
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return EFI_UNSUPPORTED;
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}
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/**
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Perform platform related reset in FSP wrapper.
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This function will reset the system with requested ResetType.
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@param[in] FspStatusResetType The type of reset the platform has to perform.
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**/
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VOID
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EFIAPI
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CallFspWrapperResetSystem (
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IN UINT32 FspStatusResetType
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)
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{
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//
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// Perform reset according to the type.
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//
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CpuDeadLoop();
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}
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