/** @file
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SysHostChipCommon.h
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@copyright
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Copyright 2016 - 2021 Intel Corporation. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _SYSHOST_CHIP_COMMON_H_
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#define _SYSHOST_CHIP_COMMON_H_
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#include <DataTypes.h>
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#include <RcVersion.h>
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//
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// CpuPciAccess
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//
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#define READ_ACCESS 0
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#define WRITE_ACCESS 1
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//
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// -----------------------------------------------------------------------------
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// Nvram structures
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//
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#pragma pack(1)
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typedef union {
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struct {
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UINT32 Bit0:1;
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UINT32 Bit1:1;
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UINT32 Bit2:1;
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UINT32 Bit3:1;
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UINT32 Bit4:1;
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UINT32 Bit5:1;
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UINT32 Bit6:1;
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UINT32 Bit7:1;
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UINT32 Bit8:1;
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UINT32 Bit9:1;
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UINT32 Bit10:1;
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UINT32 Bit11:1;
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UINT32 Bit12:1;
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UINT32 Bit13:1;
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UINT32 Bit14:1;
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UINT32 Bit15:1;
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UINT32 Bit16:1;
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UINT32 Bit17:1;
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UINT32 Bit18:1;
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UINT32 Bit19:1;
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UINT32 Bit20:1;
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UINT32 Bit21:1;
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UINT32 Bit22:1;
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UINT32 Bit23:1;
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UINT32 Bit24:1;
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UINT32 Bit25:1;
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UINT32 Bit26:1;
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UINT32 Bit27:1;
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UINT32 Bit28:1;
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UINT32 Bit29:1;
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UINT32 Bit30:1;
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UINT32 Bit31:1;
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} Bits;
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UINT32 Data;
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} DUMMY_REG;
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//
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// -----------------------------------------------------------------------------
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// Nvram structures
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//
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struct commonNvram {
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UINT64_STRUCT cpuFreq;
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RC_VERSION RcVersion; // Version of the reference code last executed
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UINT8 platformType;
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DUMMY_REG TsegBase;
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DUMMY_REG TsegLimit;
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DUMMY_REG MeMemLowBaseAddr;
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DUMMY_REG MeMemHighBaseAddr;
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DUMMY_REG MeMemLowLimit;
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DUMMY_REG MeMemHighLimit;
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DUMMY_REG MeNcMemLowBaseAddr;
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DUMMY_REG MeNcMemHighBaseAddr;
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DUMMY_REG MeNcMemLowLimit;
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DUMMY_REG MeNcMemHighLimit;
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DUMMY_REG MeNcMemLowRac;
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DUMMY_REG MeNcMemLowWac;
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UINT32 IeRequestedSize;
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DUMMY_REG IeMemLowBaseAddr;
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DUMMY_REG IeMemHighBaseAddr;
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DUMMY_REG IeMemLowLimit;
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DUMMY_REG IeMemHighLimit;
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DUMMY_REG IeNcMemLowBaseAddr;
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DUMMY_REG IeNcMemHighBaseAddr;
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DUMMY_REG IeNcMemLowLimit;
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DUMMY_REG IeNcMemHighLimit;
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DUMMY_REG IeNcMemHighRac;
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DUMMY_REG IeNcMemHighWac;
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};
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#pragma pack()
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#endif // _SYSHOST_CHIP_COMMON_H_
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