/** @file
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@copyright
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Copyright 2006 - 2021 Intel Corporation. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _memhostchipcommon_h
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#define _memhostchipcommon_h
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#include "SysHostChipCommon.h"
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#include "NGNDimmPlatformCfgData.h"
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#include <MemCommon.h>
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#include <Library/MemTypeLib.h>
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#define MAX_MEM_SS 8 // Max Memory Subsystems per socket
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#define MAX_CLUSTERS 4 // Maximum number of clusters supported
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#define MC_MAX_NODE (MAX_SOCKET * MAX_IMC) // Max number of memory nodes
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#define MAX_DIMM 2 // Max DIMM per channel
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#define MAX_DDRT_DIMM_PER_CH 1 // Max DDRT DIMM per channel
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#define MAX_UNIQUE_NGN_DIMM_INTERLEAVE 2 // Max number of unique interleaves for NGN DIMM
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#define MAX_BITS 72 // Max number of data bits per rank
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#define MAX_TECH 19 // Number of entries in DRAM technology table
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#define MAX_TECH_DDRT 8
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#define TAD_RULES 8 // Number of near memory TAD rule registers
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#define FM_TAD_RULES 12 // Number of far memory TAD rule registers
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#define FM_TAD_RULES_10NM 4 // Number of far memory only TAD rule registers in 10nm
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#define MAX_TAD_RULES (TAD_RULES + FM_TAD_RULES) // Number of combined near and far TAD rules
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#define MAX_TAD_RULES_10NM (TAD_RULES + FM_TAD_RULES_10NM) // Number of combined near and far TAD rules in 10nm
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#define MAX_TAD_WAYS 3 // Number of interleave ways for TAD RULES
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#define MAX_RT_WAYS 8 // Max. interleave ways for DDR/DDRT RTs in 256B McChan granularity
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#define MAX_RT 2 // Number of RTs per route table type
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#define MAX_FPGA_REMOTE_SAD_RULES 2 // Maximum FPGA sockets exists on ICX platform
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#define MAX_STROBE 18 // Number of strobe groups
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#define MAX_RANK_DIMM_3DS 2 // Max physical CS ranks per 3DS DIMM
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#define MAX_SUBRANK_3DS 4 // Max logical C[2:0] subranks per CS in 3DS DIMM
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#define MAX_SPARE_RANK 2 // Max number of spare ranks in a channel
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#define MAX_SUBRANK 2 // Max subranks per logical rank
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#define SPD_MODULE_PART_DDR4 20 // Number of bytes of module part - DDR4
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#define SPD_MODULE_SERIAL 4 // Number of bytes of Module Serial Number
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#define MAX_PARTIAL_MIRROR 4 //Maximum number of partial mirror regions that can be created
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#define CONVERT_64MB_TO_4KB_GRAN 14
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#define CONVERT_4KB_TO_64MB_GRAN 14
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#define CONVERT_64MB_TO_GB_GRAN 4
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#define CONVERT_GB_TO_64MB_GRAN 4
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#define CONVERT_64MB_TO_MB_GRAN 6
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#define CONVERT_MB_TO_64MB_GRAN 6
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#define CONVERT_64MB_TO_4GB_GRAN 6
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#define CONVERT_4GB_TO_64MB_GRAN 6
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#define CONVERT_64MB_TO_32GB_GRAN 9
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#define CONVERT_64B_TO_64MB 20
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#define CONVERT_B_TO_MB 20
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#define CONVERT_MB_TO_B 20
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#define CONVERT_B_TO_64MB 26
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#define CONVERT_64MB_TO_B 26
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#define CONVERT_64MB_TO_128MB_GRAN 1
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#define CONVERT_256MB_TO_64MB_GRAN 2
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#define CONVERT_64MB_TO_256MB_GRAN 2
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#define CONVERT_B_TO_256MB_GRAN 28
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#define MEM_1GB_AT_64MB_GRAN 0x10
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#define MEM_1GB_AT_4KB_GRAN 0x40000
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#define GB_TO_MB_CONVERSION 1024
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#define BITMAP_CH0_CH1_CH2 ( ( BIT0 ) | (BIT1 ) | (BIT2) )
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#define BITMAP_CH0_CH1 ( ( BIT0 ) | (BIT1 ) )
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#define BITMAP_CH1_CH2 ( ( BIT1 ) | (BIT2 ) )
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#define BITMAP_CH0_CH2 ( ( BIT0 ) | (BIT2 ) )
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#define BITMAP_CH0 BIT0
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#define BITMAP_CH1 BIT1
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#define BITMAP_CH2 BIT2
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#define CONVERT_64MB_TO_BYTE 64 * 1024 * 1024
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//
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// Define the WDB line. The WDB line is like the cache line.
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//
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#define MRC_WDB_LINES 32
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#define MRC_WDB_LINE_SIZE 64
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#define MAX_PHASE_IN_FINE_ADJUSTMENT 64
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#define MAX_PHASE_IN_READ_ADJ_DQ_RX_DFE 152 // larger range for added DQ 1/16 PI adjustments
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#pragma pack(1)
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typedef struct TADTable {
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UINT8 Enable; // Rule enable
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UINT8 SADId; // SAD Index
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UINT8 socketWays; // Socket Interleave ways for TAD
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UINT8 NmTadIndex; // Index of near memory TAD
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UINT8 FmTadIndex; // Index of far memory TAD
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UINT32 Limit; // Limit of the current TAD entry
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UINT8 TargetGran; // MC granularity of 1LM forward and 2LM forward/reverse address decoding.
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UINT8 ChGran; // Channel granularity of 1LM forward and 2LM forward/reverse address decoding.
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} TAD_TABLE;
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typedef struct SADTable {
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UINT8 Enable; // Rule enable
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MEM_TYPE type; // Bit map of memory region types, See defines 'MEM_TYPE_???' above for bit definitions of the ranges.
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UINT8 granularity; // Interleave granularities for current SAD entry. Possible interleave granularity options depend on the SAD entry type. Note that SAD entry type BLK Window and CSR/Mailbox/Ctrl region do not support any granularity options
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UINT32 Base; // Base of the current SAD entry
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UINT32 Limit; // Limit of the current SAD entry
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UINT8 ways; // Interleave ways for SAD
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UINT8 channelInterBitmap[MAX_IMC]; //Bit map to denote which DDR4/NM channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 011b denotes Ch1 & 0 are interleaved
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UINT8 FMchannelInterBitmap[MAX_IMC]; //Bit map to denote which FM channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 011b denotes Ch1 & 0 are interleaved
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UINT8 NmChWays; // Channel Interleave ways for SAD. Represents channelInterBitmap ways for DDR4/NM.
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UINT8 FmChWays; // Channel Interleave ways for SAD. Represents FMchannelInterBitmap ways for DDRT.
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UINT8 imcInterBitmap; // Bit map to denote which IMCs are interleaved from this socket.
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UINT8 NmImcInterBitmap; // Bit map to denote which IMCs are interleaved from this socket as NM (10nm usage only).
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BOOLEAN local; //0 - Remote 1- Local
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UINT8 IotEnabled; // To indicate if IOT is enabled
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UINT8 mirrored; //To Indicate the SAD is mirrored while enabling partial mirroring
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UINT8 Attr;
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UINT8 tgtGranularity; // Interleave mode for target list
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UINT8 Cluster; // SNC cluster, hemisphere, or quadrant index.
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} SAD_TABLE;
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typedef struct IMC {
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UINT8 imcEnabled[MAX_IMC];
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UINT8 imcNum; // imc Number
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UINT32 memSize; // DDR4 memory size for this imc (64MB granularity)
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UINT32 NVmemSize; // NV Memory size of this ha
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UINT32 volSize; // Volatile size of the NVM dimms for this imc (64MB granularity)
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UINT32 NonVolSize; // Non-Volatile size of the NVM DIMMs for this iMC (64MB granularity)
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UINT32 perSize; // Persistent size of the NVM dimms for this imc (64MB granularity)
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UINT32 WbCachePerSize; // Persistent WB cache (AD-WB) size of the NVM dimms for this imc (64MB granularity)
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UINT8 TADintList[MAX_TAD_RULES][MAX_TAD_WAYS]; // TAD interleave list for this socket
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UINT8 TADChnIndex[MAX_TAD_RULES][MAX_TAD_WAYS]; // Corresponding TAD channel indexes (per channel)
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INT32 TADOffset[MAX_TAD_RULES][MAX_TAD_WAYS]; // Corresponding TAD offsets (per channel)
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TAD_TABLE TAD[MAX_TAD_RULES]; // TAD table
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UINT8 imcChannelListStartIndex; // Index in channel list of first channel on this imc
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} IMC_INFO_STRUCT;
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typedef struct firmwareRev {
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UINT8 majorVersion;
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UINT8 minorVersion;
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UINT8 hotfixVersion;
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UINT16 buildVersion;
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} FIRMWARE_REV;
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typedef struct Reserved168 {
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UINT8 Reserved79;
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UINT8 Reserved80;
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UINT8 Reserved83;
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UINT8 Reserved86[MAX_SOCKET * MAX_IMC];
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UINT8 Reserved89;
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UINT8 Reserved87;
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UINT8 Reserved148;
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} MEM_RESERVED_1;
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#pragma pack()
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#define MAX_SI_SOCKET 8 // Maximum silicon supported socket number
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typedef struct {
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UINT32 BlockDecoderBase; // 64MB unit
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UINT32 BlockDecoderLimit;
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UINT8 BlockSocketEnable;
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UINT8 BlockMcChEn[MAX_SI_SOCKET][MAX_IMC][MAX_MC_CH];
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} MEMORY_MAP_BLOCK_DECODER_DATA;
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//
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// Chip specific section of struct Socket
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//
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#define SOCKET_CHIP \
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struct SADTable SAD[MAX_DRAM_CLUSTERS * MAX_SAD_RULES]; \
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UINT8 DdrtChRouteTable[MAX_RT][MAX_RT_WAYS]; /* PMEM/BLK memory channel route table 2 for CR protocol */ \
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UINT8 DdrtTgtRouteTable[MAX_RT][MAX_RT_WAYS]; /* PMEM/BLK memory target route table 2 for CR protocol */ \
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struct IMC imc[MAX_IMC]; \
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UINT8 ddrClkData; \
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UINT8 ddrClkType; \
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UINT8 ddrFreqCheckFlag; \
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UINT8 SktSkuValid; \
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UINT32 SktSkuLimit; \
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UINT32 SktTotMemMapSPA; \
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UINT32 SktPmemMapSpa; \
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UINT32 SktMemSize2LM; \
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UINT8 maxFreq; \
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UINT8 clkSwapFixDis; \
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UINT8 ioInitdone;
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#endif // _memhostchipcommon_h
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