/** @file
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Data format for Ioh Memory Config Data Structure
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@copyright
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Copyright 1999 - 2021 Intel Corporation. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef __SOCKET_MEMORY_CONFIG_DATA_H__
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#define __SOCKET_MEMORY_CONFIG_DATA_H__
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#include <UncoreCommonIncludes.h>
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#include <MemDefaults.h>
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extern EFI_GUID gEfiSocketMemoryVariableGuid;
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#define SOCKET_MEMORY_CONFIGURATION_NAME L"SocketMemoryConfig"
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#pragma pack(1)
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typedef struct {
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UINT8 ReservedS48;
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UINT8 MemoryHotPlugBase;
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UINT8 MemoryHotPlugLen;
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UINT8 Srat;
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UINT8 SratMemoryHotPlug;
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UINT8 SratCpuHotPlug;
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UINT8 PagePolicy;
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UINT8 PatrolScrub;
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UINT8 PatrolScrubDuration;
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UINT8 TempRefreshOption;
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UINT8 HalfxRefreshValue;
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UINT8 TwoxRefreshValue;
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UINT8 FourxRefreshValue;
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UINT8 NsddcEn;
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UINT8 EsddcEn;
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UINT8 ColumnCorrectionDisable;
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UINT8 SaiPolicyGroupWaBiosW;
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UINT8 PatrolScrubAddrMode;
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UINT8 partialmirrorsad0;
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UINT8 PartialMirrorUefi;
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UINT16 PartialMirrorUefiPercent;
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UINT16 partialmirrorsize[MAX_PARTIAL_MIRROR]; // Array of sizes of different partial mirrors
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UINT8 ImmediateFailoverAction;
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UINT8 PlusOneEn;
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UINT8 MemCeFloodPolicy;
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UINT16 spareErrTh;
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UINT8 TriggerSWErrThEn;
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UINT16 SpareSwErrTh;
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UINT16 timeWindow;
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UINT8 DieSparing;
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UINT8 PclsEn;
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UINT8 ADDDCEn;
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UINT8 DcpmmEccModeSwitch;
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UINT8 AdddcErrInjEn;
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UINT8 leakyBktTimeWindow;
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UINT8 leakyBktLo;
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UINT8 leakyBktHi;
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UINT16 leakyBktHour;
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UINT8 leakyBktMinute;
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UINT8 CmdNormalization;
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UINT8 LrDimmBacksideVrefEn;
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UINT8 CmdVrefEnable;
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UINT8 DramRonEn;
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UINT8 McRonEn;
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UINT8 RxCtleTrnEn;
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UINT8 RxOdtEn;
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UINT8 LrDimmWrVrefEn;
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UINT8 LrDimmRdVrefEn;
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UINT8 LrDimmTxDqCentering;
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UINT8 LrDimmRxDqCentering;
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UINT8 txEqCalibration;
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UINT8 CmdTxEqCalibration;
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UINT8 RxDfe;
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UINT8 TxRiseFallSlewRate;
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UINT8 iModeTraining;
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UINT8 TcoCompTraining;
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UINT8 RoundTripLatency;
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UINT8 DutyCycleTraining;
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UINT8 PxcTraining;
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UINT8 DdjcTraining;
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UINT8 refreshMode;
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UINT8 dllResetTestLoops;
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UINT8 DdrMemoryType;
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UINT8 HwMemTest;
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UINT16 MemTestLoops;
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UINT8 TrainingResultOffsetFunctionEnable;
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UINT16 OffsetTxDq;
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UINT16 OffsetRxDq;
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UINT16 OffsetTxVref;
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UINT16 OffsetRxVref;
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UINT16 OffsetCmdAll;
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UINT16 OffsetCmdVref;
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UINT16 OffsetCtlAll;
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UINT32 AdvMemTestOptions;
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UINT8 AdvMemTestResetList;
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UINT8 AdvMemTestCondition;
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UINT16 AdvMemTestCondVdd;
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UINT8 AdvMemTestCondTwr;
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UINT16 AdvMemTestCondTrefi;
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UINT32 AdvMemTestCondPause;
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UINT8 EccSupport;
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UINT8 EccEnable;
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UINT8 ReservedS49;
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UINT8 ReservedS50;
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UINT8 ReservedS51;
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UINT8 ReservedS52;
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UINT16 ReservedS53;
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UINT16 ReservedS54;
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UINT16 ReservedS55;
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UINT16 ReservedS56;
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UINT16 ReservedS57;
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UINT8 ReservedS58;
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UINT16 ReservedS59;
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UINT8 ReservedS60;
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UINT16 ReservedS61;
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UINT8 ReservedS62;
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UINT8 ReservedS63;
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UINT16 ReservedS64;
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UINT16 ReservedS65;
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UINT8 ReservedS66;
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UINT8 ReservedS67;
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UINT8 ReservedS68;
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UINT8 ReservedS69;
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UINT8 ReservedS70;
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UINT8 ReservedS71;
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UINT8 ReservedS72;
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UINT8 ReservedS73;
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UINT8 ReservedS74[16]; //[MAX_SOCKET * MAX_IMC] = [8]
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UINT8 volMemMode;
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UINT8 CacheMemType; //Only valid if volMemMode is 2LM
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UINT8 DdrCacheSize;
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UINT8 PmemCaching;
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UINT8 ReservedS75;
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UINT8 memInterleaveGran1LM;
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UINT8 ReservedS76;
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UINT8 ReservedS77;
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UINT8 ReservedS78;
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UINT8 ReservedS79;
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UINT8 ReservedS80;
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UINT8 CkeProgramming;
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UINT8 SrefProgramming;
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UINT8 PkgcSrefEn;
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UINT8 CkeIdleTimer;
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UINT8 ApdEn;
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UINT8 PpdEn;
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UINT8 DdrtCkeEn;
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UINT8 OppSrefEn;
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UINT8 OppSrefVisible; //Setup variable to hide Opportunistic Self Refresh Knob
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UINT8 DdrtSrefEn;
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UINT8 DataDllOff;
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UINT8 MdllOffEn;
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UINT8 CkMode;
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UINT8 MemTestOnColdFastBoot;
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UINT8 AttemptFastBoot;
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UINT8 AttemptFastBootCold;
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UINT8 bdatEn;
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UINT8 ScrambleEnDDRT;
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UINT8 ScrambleEn; // for ddr4
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UINT8 allowCorrectableError;
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UINT8 allowCorrectableMemTestError;
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UINT16 ScrambleSeedLow;
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UINT16 ScrambleSeedHigh;
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UINT8 CustomRefreshRateEn;
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UINT8 CustomRefreshRate;
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UINT8 readVrefCenter;
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UINT8 wrVrefCenter;
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UINT8 haltOnMemErr;
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UINT8 thermalthrottlingsupport;
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UINT8 MemTripReporting;
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UINT8 OffPkgMemToThermTrip;
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UINT8 OffPkgMemToMemTrip;
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UINT8 InPkgMemToThermTrip;
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UINT8 InPkgMemToMemTrip;
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UINT8 DimmTempStatValue;
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UINT8 XMPProfilesSup;
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UINT8 XMPMode;
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UINT8 tCAS;
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UINT8 tRP;
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UINT8 tRCD;
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UINT8 tRAS;
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UINT8 tWR;
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UINT16 tRFC;
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UINT8 tRRD;
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UINT8 tRRD_L;
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UINT8 tRTP;
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UINT8 tWTR;
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UINT8 tFAW;
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UINT8 tCWL;
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UINT8 tRC;
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UINT8 commandTiming;
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UINT16 tREFI;
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UINT8 DdrFreqLimit;
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UINT16 Vdd;
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UINT8 lrdimmModuleDelay;
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UINT32 rmtPatternLength;
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UINT32 rmtPatternLengthExt;
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UINT8 RecEnDelayAverage;
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UINT8 check_pm_sts;
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UINT8 check_platform_detect;
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UINT8 MemPwrSave;
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UINT8 ElectricalThrottlingMode;
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UINT8 MultiThreaded;
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UINT8 promoteMrcWarnings;
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UINT8 promoteWarnings;
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UINT8 oppReadInWmm;
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UINT16 normOppInterval;
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UINT8 ReservedS81[96]; //[MAX_SETUP_SOCKET * MAX_SETUP_IMC * MAX_SETUP_MC_CH] = [8 * 4 * 3 = 96]
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UINT8 mdllSden;
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UINT8 memhotSupport;
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UINT8 MemHotIn;
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UINT8 MemHotOut;
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UINT8 MemHotOuputAssertThreshold;
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UINT8 ADREn;
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UINT8 RankMargin;
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UINT8 EnableBacksideRMT;
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UINT8 EnableBacksideCMDRMT;
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UINT8 EnableNgnBcomMargining;
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UINT8 ReservedS82;
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UINT8 RankSparing;
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UINT8 multiSparingRanks;
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UINT8 ReservedS83;
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UINT8 dimmIsolation;
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UINT8 smbSpeed;
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UINT8 SmbSpdAccess;
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UINT8 SpdPrintEn;
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UINT16 SpdPrintLength;
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UINT8 EnforcePOR;
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UINT8 pda;
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UINT8 turnaroundOpt;
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UINT8 turnaroundOptDdrt;
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UINT8 oneRankTimingMode;
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UINT8 eyeDiagram;
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UINT8 NvmdimmPerfConfig;
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UINT8 ReservedS84;
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UINT8 ReservedS85;
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UINT8 ReservedS86;
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UINT8 ReservedS87;
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UINT8 ReservedS88;
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UINT8 ReservedS89;
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UINT8 ReservedS90;
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UINT8 ReservedS91;
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UINT8 ReservedS92;
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UINT8 ReservedS93;
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UINT8 ReservedS94;
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UINT8 ReservedS95;
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UINT8 ReservedS96;
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UINT8 ReservedS97;
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UINT8 ReservedS98;
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UINT8 ReservedS99;
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UINT8 ReservedS100;
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UINT8 ReservedS101;
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UINT8 ReservedS102;
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UINT8 ReservedS103;
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UINT8 ReservedS104;
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UINT8 DramRaplPwrLimitLockCsr;
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UINT8 DramRaplEnable;
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UINT8 BwLimitTfOvrd;
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UINT8 perbitmargin;
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UINT8 DramRaplExtendedRange;
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UINT8 CmsEnableDramPm;
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UINT8 logParsing;
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UINT8 WritePreamble;
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UINT8 ReadPreamble;
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UINT8 WrCRC;
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UINT8 AepOnSystem;
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UINT8 EkvOnSystem; // 0 => Do not suppress power management policy for BWV, 1 => suppress power management policy for BWV.
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UINT8 BwvOnSystem; // 0 => Do not suppress power management policy for EKV, 1 => suppress power management policy for EKV.
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// NGN options
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UINT8 LockNgnCsr;
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UINT8 NgnCmdTime;
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UINT8 NgnEccCorr;
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UINT8 NgnEccWrChk;
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UINT8 NgnEccRdChk;
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UINT8 NgnEccExitCorr;
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UINT8 NgnDebugLock;
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UINT8 NgnArsPublish;
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UINT8 RmtOnColdFastBoot;
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UINT8 LegacyRmt;
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UINT8 mrcRepeatTest;
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UINT8 ReservedS105;
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UINT8 ReservedS106;
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UINT8 ReservedS107;
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UINT8 staggerref;
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UINT32 memFlows;
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UINT32 memFlowsExt;
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UINT32 memFlowsExt2;
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UINT32 memFlowsExt3;
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UINT8 Blockgnt2cmd1cyc;
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UINT8 TrefiPerChannel;
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UINT8 TrefiNumofRank;
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UINT16 TrefiDelay;
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UINT8 Disddrtopprd;
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UINT16 Reserved;
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UINT8 setSecureEraseAllDIMMs;
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UINT8 setSecureEraseSktCh[64]; // [MAX_SOCKET * MAX_IMC * MAX_MC_CH]
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UINT8 SetSecureEraseSktChHob[64]; // [MAX_SOCKET * MAX_IMC * MAX_MC_CH]
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UINT8 AppDirectMemoryHole;
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UINT8 LatchSystemShutdownState;
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UINT8 ExtendedType17;
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//
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// PPR related
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//
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UINT8 pprType;
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UINT8 pprErrInjTest;
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// CR QoS Configuration Profiles
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UINT8 FastGoConfig;
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UINT8 ReservedS108;
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UINT8 LegacyADRModeEn;
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UINT8 MinNormalMemSize;
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UINT8 ADRDataSaveMode;
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UINT8 eraseArmNVDIMMS;
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UINT8 restoreNVDIMMS;
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UINT8 interNVDIMMS;
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UINT8 imcBclk;
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UINT8 spdCrcCheck;
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UINT8 ReservedS109;
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UINT8 SETUP_REMOVE_SanitizeOverwriteNvmDimm; // removed
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UINT8 EliminateDirectoryInFarMemory;
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UINT8 NvmdimmPowerCyclePolicy;
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//CMI Init option
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UINT8 CmiInitOption;
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//
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// Cmd setup hold percent offset for 2n timing
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//
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UINT8 cmdSetupPercentOffset;
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UINT8 ShortStroke2GB;
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UINT8 NvDimmEnergyPolicy; //Energy Policy Management
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UINT8 ReservedS110;
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UINT8 ReservedS111;
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UINT8 ReservedS112;
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UINT8 ReservedS113;
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UINT8 DisableDirForAppDirect;
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UINT8 NvmMediaStatusException;
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UINT8 NvmQos;
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UINT8 ReservedS114;
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UINT8 ReservedS115;
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UINT8 ReservedS116;
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//
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// FIS 2.x
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//
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UINT16 DcpmmAveragePowerLimit; // Power limit in mW used for averaged power ( Valid range starts from 10000mW).
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UINT8 DcpmmAveragePowerTimeConstant; // Value used as a base time window for power usage measurements Turbo Mode Support(in mSec).
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UINT32 DcpmmMbbAveragePowerTimeConstant; // Value used as a base time window for power usage measurements Memory Bandwidth Boost Support(in mSec).
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UINT8 DcpmmMbbFeature; // Allows enabling and disabling the feature (Turbo Mode State/Memory Bandwidth Boost).
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UINT16 DcpmmMbbMaxPowerLimit; // Power limit in mW used for limiting the Turbo Mode/Memory Bandwidth Boost
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// power consumption (Valid range starts from 15000mW).
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UINT8 ReservedS117;
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UINT8 ReservedS118;
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UINT8 ReservedS119;
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UINT8 ReservedS120;
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UINT8 LsxImplementation;
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UINT8 FactoryResetClear;
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UINT8 EadrSupport;
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UINT32 NvdimmSmbusMaxAccessTime;
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UINT32 NvdimmSmbusReleaseDelay;
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UINT8 NfitPublishMailboxStructs;
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//
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// fADR setup option
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//
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UINT8 FadrSupport;
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//
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// Biased 2-way near memory cache support options
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//
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UINT8 EnableTwoWayNmCache; // Enable or disable biased 2-way near memory cache.
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UINT16 NonPreferredWayMask; // A 10-bit mask to control the bias counter ratio.
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UINT8 PreferredReadFirst; // Reads are issued to the non-preferred or preferred way first.
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//
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// Boot-time fast zero memory setup option
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//
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UINT8 FastZeroMemSupport; // Enable or disable boot-time fast zero memory support.
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//
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// XOR decoder options
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//
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UINT8 ReservedS121;
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UINT8 ReservedS122;
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UINT8 ReservedS123;
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UINT8 ReservedS124;
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UINT8 ReservedS125;
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UINT8 ReservedS126;
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UINT8 ReservedS127;
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UINT8 ReservedS128;
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UINT8 ReservedS129;
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UINT8 ReservedS130;
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UINT16 ReservedS131;
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UINT8 ReservedS132;
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UINT8 ReservedS133;
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UINT8 ReservedS134;
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UINT8 ReservedS135;
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UINT8 DcpmmApiVersion200OnSystem; // 0 => Suppress DcpmmAveragePowerTimeConstant, 1 => Do not suppress DcpmmAveragePowerTimeConstant.
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UINT8 DcpmmApiVersion201OnSystem; // 0 => Suppress DcpmmAveragePowerTimeConstant, 1 => Do not suppress DcpmmAveragePowerTimeConstant.
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UINT8 DcpmmApiVersion200OrGreaterOnSystem;
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UINT8 ReservedS136;
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UINT8 EnforcePopulationPor;
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//
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// DFE Path Finding
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//
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UINT8 EnableTapSweep;
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UINT8 DfeGainBias;
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UINT8 Tap1Start;
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UINT8 Tap1End;
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UINT8 Tap1Size;
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UINT8 Tap2Start;
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UINT8 Tap2End;
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UINT8 Tap2Size;
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UINT8 Tap3Start;
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UINT8 Tap3End;
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UINT8 Tap3Size;
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UINT8 Tap4Start;
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UINT8 Tap4End;
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UINT8 Tap4Size;
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UINT8 TrainingCompOptions; // Memory Training Comp Options Values.
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UINT8 PeriodicRcomp; // Memory Periodic Rcomp Auto/Enable/Disable.
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UINT8 PeriodicRcompInterval; // Memory Periodic Rcomp Interval.
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UINT8 ReservedS137;
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UINT8 AepNotSupportedException;
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UINT8 ReservedS138;
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UINT8 ReservedS139;
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UINT8 PanicWm;
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UINT16 OffsetRecEn;
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UINT8 EadrCacheFlushMode;
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UINT8 ReservedS140;
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UINT8 ReservedS141;
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UINT8 ReservedS142;
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UINT8 ReservedS143;
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UINT8 ReservedS144;
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UINT8 ReservedS145;
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UINT8 LrdimmDbDfeTraining;
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UINT8 ReservedS146;
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UINT8 ReservedS147;
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UINT8 ReservedS148;
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UINT8 AdvMemTestRetryAfterRepair;
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UINT8 AdvMemTestPpr;
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UINT8 AdvMemTestRankListNumEntries;
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UINT32 AdvMemTestRankList[ADV_MT_LIST_LIMIT];
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UINT32 SmartTestKey;
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UINT8 SetMemTested;
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//
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// RMT minimum margin check
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//
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UINT8 RmtMinimumMarginCheck;
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UINT8 ReservedS149;
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} SOCKET_MEMORY_CONFIGURATION;
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#pragma pack()
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#endif
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